公开(公告)号：US12255234B2

公开(公告)日：2025-03-18

申请号：US18409509

申请日：2024-01-10

Applicant: Intel Corporation

Inventor： Siddharth Chouksey ,  Glenn Glass ,  Anand Murthy ,  Harold Kennel ,  Jack T. Kavalieros ,  Tahir Ghani ,  Ashish Agrawal ,  Seung Hoon Sung

IPC: H01L31/072 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L31/109

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

公开(公告)号：US12211794B2

公开(公告)日：2025-01-28

申请号：US17648821

申请日：2022-01-25

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Ashish Agrawal ,  Kevin Lin ,  Abhishek Anil Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L29/24 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H01L21/285

Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.

公开(公告)号：US11996404B2

公开(公告)日：2024-05-28

申请号：US17540120

申请日：2021-12-01

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

IPC: H01L27/06 ,  H01L21/683 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L27/0688 ,  H01L21/6835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/1033 ,  H01L2221/68363

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.

公开(公告)号：US11923421B2

公开(公告)日：2024-03-05

申请号：US17869622

申请日：2022-07-20

Applicant: Intel Corporation

Inventor： Siddharth Chouksey ,  Glenn Glass ,  Anand Murthy ,  Harold Kennel ,  Jack T. Kavalieros ,  Tahir Ghani ,  Ashish Agrawal ,  Seung Hoon Sung

IPC: H01L31/072 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L31/109

CPC classification number: H01L29/165 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

公开(公告)号：US11830788B2

公开(公告)日：2023-11-28

申请号：US17303270

申请日：2021-05-25

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Ashish Agrawal ,  Urusa Alaan ,  Christopher Jezewski ,  Mauro Kobrinsky ,  Kevin Lin ,  Abhishek Anil Sharma

IPC: H01L23/40 ,  H01L21/822 ,  H01L23/532 ,  H01L27/12 ,  H01L21/70

CPC classification number: H01L23/4012 ,  H01L21/707 ,  H01L21/8221 ,  H01L23/5329 ,  H01L27/1222

Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.

公开(公告)号：US11721766B2

公开(公告)日：2023-08-08

申请号：US17701232

申请日：2022-03-22

Applicant: Intel Corporation

Inventor： Van H. Le ,  Ashish Agrawal ,  Seung Hoon Sung ,  Abhishek A. Sharma ,  Ravi Pillarisetty

IPC: H01L29/786 ,  C30B29/08 ,  C30B29/40 ,  H01L27/088

CPC classification number: H01L29/78654 ,  C30B29/08 ,  C30B29/40 ,  H01L27/088

Abstract: Described herein are apparatuses, systems, and methods associated with metal-assisted transistors. A single crystal semiconductor material may be seeded from a metal. The single crystal semiconductor material may form a channel region, a source, region, and/or a drain region of the transistor. The metal may form the source contact or drain contact, and the source region, channel region, and drain region may be stacked vertically on the source contact or drain contact. Alternatively, a metal-assisted semiconductor growth process may be used to form a single crystal semiconductor material on a dielectric material adjacent to the metal. The portion of the semiconductor material on the dielectric material may be used to form the transistor. Other embodiments may be described and claimed.

公开(公告)号：US11670588B2

公开(公告)日：2023-06-06

申请号：US16243790

申请日：2019-01-09

Applicant: Intel Corporation

Inventor： Christopher Jezewski ,  Ashish Agrawal ,  Kevin L. Lin ,  Abhishek Sharma ,  Carl Naylor ,  Urusa Alaan

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/12 ,  H01L29/417 ,  H01L29/24 ,  H01L29/423 ,  H01L29/786 ,  H01L23/535 ,  H01L21/768 ,  H01L29/66 ,  H01L21/02 ,  H01L21/4763

CPC classification number: H01L23/528 ,  H01L21/02568 ,  H01L21/47635 ,  H01L21/76802 ,  H01L23/5226 ,  H01L23/535 ,  H01L27/124 ,  H01L27/1222 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/78642 ,  G05B2219/1163

Abstract: Integrated circuits including selectable vias are disclosed. The techniques are particularly well-suited to back end of line (BEOL) processes. In accordance with some embodiments, a selectable via includes a vertically-oriented thin film transistor structure having a wrap around gate, which can be used to effectively select (or deselect) the selectable via ad hoc. When a selectable via is selected, a signal is allowed to pass through the selectable via. Conversely, when the selectable via is not selected, a signal is not allowed to pass through the selectable via. The selectable characteristic of the selectable via allows multiple vias to share a global interconnect. The global interconnect can be connected to any number of selectable vias, as well as standard vias.

公开(公告)号：US20230145229A1

公开(公告)日：2023-05-11

申请号：US17522342

申请日：2021-11-09

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ashish Agrawal ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Ehren Mannebach ,  Willy Rachmady ,  Marko Radosavljevic

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/78696 ,  H01L27/088

Abstract: Techniques are provided herein to form semiconductor devices having backside contacts. Sacrificial plugs are formed first within a substrate at particular locations to align with source and drain regions during a later stage of processing. Another wafer is subsequently bonded to the surface of the substrate and is thinned to effectively transfer different material layers to the top surface of the substrate. One of the transferred layers acts as a seed layer for the growth of additional semiconductor material used to form semiconductor devices. The source and drain regions of the semiconductor devices are sufficiently aligned over the previously formed sacrificial plugs. A backside portion of the substrate may be removed to expose the sacrificial plugs from the backside. Removal of the plugs and replacement of the recesses left behind with conductive material forms the conductive backside contacts to the source or drain regions.

公开(公告)号：US20230141914A1

公开(公告)日：2023-05-11

申请号：US17523711

申请日：2021-11-10

Applicant: Intel Corporation

Inventor： Ashish Agrawal ,  Anand Murthy ,  Jack T. Kavalieros ,  Rajat K. Paul ,  Gilbert Dewey ,  Susmita Ghose ,  Seung Hoon Sung

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/161

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/78696 ,  H01L29/161

Abstract: Techniques are provided herein to form semiconductor devices having nanowires with an increased strain. A thin layer of silicon germanium or germanium tin can be deposited over one or more suspended nanoribbons. An anneal process may then be used to drive the silicon germanium or germanium tin throughout the one or more semiconductor nanoribbons, thus forming one or more nanoribbons with a changing material composition along the lengths of the one or more nanoribbons. In some examples, at least one of the one or more nanoribbons includes a first region at one end of the nanoribbon having substantially no germanium, a second region at the other end of the nanoribbon having substantially no germanium, and a third region between the first and second regions having a substantially uniform non-zero germanium concentration. The change in material composition along the length of the nanoribbon imparts a compressive strain.

公开(公告)号：US11476164B2

公开(公告)日：2022-10-18

申请号：US16631352

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Ying Pang ,  Florian Gstrein ,  Dan S. Lavric ,  Ashish Agrawal ,  Robert Niffenegger ,  Padmanava Sadhukhan ,  Robert W. Heussner ,  Joel M. Gregie

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66

Abstract: Integrated circuit structures having differentiated workfunction layers are described. In an example, an integrated circuit structure includes a first gate electrode above a substrate. The first gate electrode includes a first workfunction material layer. A second gate electrode is above the substrate. The second gate electrode includes a second workfunction material layer different in composition from the first workfunction material layer. The second gate electrode does not include the first workfunction material layer, and the first gate electrode does not include the second workfunction material layer. A third gate electrode above is the substrate. The third gate electrode includes a third workfunction material layer different in composition from the first workfunction material layer and the second workfunction material layer. The third gate electrode does not include the first workfunction material layer and does not include the second workfunction material layer.