公开(公告)号：US20210240475A1

公开(公告)日：2021-08-05

申请号：US17124813

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： ELIEZER WEISSMANN ,  MARK CHARNEY ,  MICHAEL MISHAELI ,  ROBERT VALENTINE ,  ITAI RAVID ,  JASON W. BRANDT ,  GILBERT NEIGER ,  BARUCH CHAIKIN ,  EFRAIM ROTEM

IPC: G06F9/30 ,  G06F9/38

Abstract: Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

公开(公告)号：US20190041966A1

公开(公告)日：2019-02-07

申请号：US16025955

申请日：2018-07-02

Applicant: Intel Corporation

Inventor： EFRAIM ROTEM ,  OREN LAMDAN ,  ALON NAVEH

IPC: G06F1/32 ,  G06F12/0875 ,  G06F1/20 ,  G06F12/0862 ,  G06F9/38 ,  G06F9/30

Abstract: For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time. The plurality of processor cores are in a same package. Logic of the processor is to set one or more operating parameters for one or more of the plurality of processor cores. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. The logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set. Other embodiments are also disclosed.

公开(公告)号：US20150379668A1

公开(公告)日：2015-12-31

申请号：US14319099

申请日：2014-06-30

Applicant: Intel Corporation

Inventor： ELIEZER WEISSMANN ,  ARIK GIHON ,  EFRAIM ROTEM ,  PAUL S. DIEFENBAUGH ,  ERIC C. SAMSON ,  MICHAEL MISHAELI ,  YONI AIZIK ,  CHEN RANEL

IPC: G06T1/20 ,  G09G5/18

CPC classification number: G06F9/5044 ,  G06F3/14 ,  G06F9/5083 ,  G09G2360/08

Abstract: An apparatus and method for determining thread execution parallelism. For example, a processor in accordance with one embodiment comprises: a plurality of cores to execute a plurality of threads; a plurality of counters to collect data related to the execution of the plurality of threads on the plurality of cores; a dependency analysis module to analyze the data related to the execution of the threads and responsively determine a level of inter-thread dependency; and a control module to responsively adjust operation of the plurality of cores based on the determined level of inter-thread dependency.

Abstract translation: 一种用于确定线程执行并行性的装置和方法。 例如，根据一个实施例的处理器包括：多个核，用于执行多个线程; 多个计数器，用于收集与所述多个核上的所述多个线程的执行相关的数据; 依赖关系分析模块，用于分析与线程的执行有关的数据，并且响应地确定线程间相关性的级别; 以及控制模块，用于基于确定的线程间依赖性水平来响应地调整多个核心的操作。

公开(公告)号：US20230076318A1

公开(公告)日：2023-03-09

申请号：US17903307

申请日：2022-09-06

Applicant: Intel Corporation

Inventor： ELIEZER WEISSMANN ,  MARK CHARNEY ,  MICHAEL MISHAELI ,  ROBERT VALENTINE ,  ITAI RAVID ,  JASON W. BRANDT ,  GILBERT NEIGER ,  BARUCH CHAIKIN ,  EFRAIM ROTEM

IPC: G06F9/38 ,  G06F9/30

Abstract: Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

公开(公告)号：US20200285294A1

公开(公告)日：2020-09-10

申请号：US16880167

申请日：2020-05-21

Applicant: Intel Corporation

Inventor： DORON RAJWAN ,  EFRAIM ROTEM ,  ELIEZER WEISSMANN ,  AVINASH N. ANANTHAKRISHNAN ,  DORIT SHAPIRA

IPC: G06F1/3228 ,  G06F1/324 ,  G06F1/3237 ,  G06F1/3203

Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.

公开(公告)号：US20170293332A1

公开(公告)日：2017-10-12

申请号：US15093042

申请日：2016-04-07

Applicant: Intel Corporation

Inventor： EFRAIM ROTEM ,  TOD F. SCHIFF ,  DORON RAJWAN ,  JEFFREY M. JULL ,  JAMES G. HERMERDING, II ,  NIR ROSENZWEIG ,  MAYTAL TOLEDANO ,  ALEXANDER B. UAN-ZO-LI

IPC: G06F1/26 ,  G08B21/18

Abstract: One embodiment provides an apparatus. The apparatus includes power control logic and a critical comparator. The power control logic is to determine a critical threshold (TC) based, at least in part, on an available input power value (Pin). The critical comparator is to compare a system power consumption value (Psys) and the critical threshold and to assert a processor critical throttle signal to a processor if the system power consumption value is greater than or equal to the critical threshold.

公开(公告)号：US20230063955A1

公开(公告)日：2023-03-02

申请号：US18048593

申请日：2022-10-21

Applicant: Intel Corporation

Inventor： DORON RAJWAN ,  EFRAIM ROTEM ,  ELIEZER WEISSMANN ,  AVINASH N. ANANTHAKRISHNAN ,  DORIT SHAPIRA

IPC: G06F1/3228 ,  G06F1/324 ,  G06F1/3237 ,  G06F1/3203

Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.

公开(公告)号：US20210018971A1

公开(公告)日：2021-01-21

申请号：US17042804

申请日：2018-05-01

Applicant: Intel Corporation

Inventor： EFRAIM ROTEM ,  ELIEZER WEISSMANN ,  ERIC DEHAEMER ,  ALEXANDER GENDLER ,  NADAV SHULMAN ,  KRISHNAKANTH SISTLA ,  NIR ROSENZWEIG ,  ANKUSH VARMA ,  ARIEL SZAPIRO ,  ARYE ALBAHARI ,  IDO MELAMED ,  NIR MISGAV ,  VIVEK GARG ,  NIMROD ANGEL ,  ADWAIT PURANDARE ,  ELKANA KOREM

IPC: G06F1/329 ,  G06F1/3206 ,  G06F9/48 ,  G06F9/30 ,  G06F9/4401

Abstract: A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

公开(公告)号：US20170147054A1

公开(公告)日：2017-05-25

申请号：US15426876

申请日：2017-02-07

Applicant: Intel Corporation

Inventor： HISHAM ABU SALAH ,  ELIEZER WEISSMANN ,  EFRAIM ROTEM ,  PAUL S. DIEFENBAUGH ,  JAY D. SCHWARTZ ,  SHARAD C. TRIPATHI

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3206 ,  G06F1/3293 ,  Y02D10/126

Abstract: Techniques described above may enhance the power-performance efficiency of a processor, SoC, or a computing system. Embodiments described here allow an increase in frequency of the clock signal to a peak frequency value in response to detecting an occurrence of a burst of high activity within the low processor utilization periods. A power management unit may accumulate the budget during the low or idle processor utilization periods and the level of activity of the burst of high activity signal may be determined. The PMU may increase the frequency of the clock signal provided to the processing cores if the level of the burst of high activity exceeds a first threshold value and an accumulated budget value exceeds a second threshold value.