公开(公告)号：US20230195634A1

公开(公告)日：2023-06-22

申请号：US17553476

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Krishna Ganapathy ,  Kameswar Subramaniam ,  Christopher D Bryant ,  Taylor Morrow

IPC: G06F12/0862 ,  G06F12/0831 ,  G06F9/30 ,  G06F13/16

CPC classification number: G06F12/0862 ,  G06F12/0833 ,  G06F9/30101 ,  G06F13/161 ,  G06F13/1689

Abstract: An embodiment of an integrated circuit may comprise a prefetcher, a model specific register that is accessible at runtime to store information associated with the prefetcher, and circuitry communicatively coupled to the model specific register and prefetcher to adjust a runtime operation of the prefetcher based on the information associated with the prefetcher stored in the model specific register. Other embodiments are disclosed and claimed.

公开(公告)号：US20190042280A1

公开(公告)日：2019-02-07

申请号：US15936585

申请日：2018-03-27

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Avinash N. Ananthakrishnan ,  Eugene Gorbatov ,  Russell Fenger ,  Ashok Raj ,  Kameswar Subramaniam

IPC: G06F9/445 ,  G06F11/34 ,  G06F11/30

Abstract: In one embodiment, a processor includes a plurality of cores to execute instructions, a first identification register having a first field to store a feedback indicator to indicate to an operating system (OS) that the processor is to provide hardware feedback information to the OS dynamically and a power controller coupled to the plurality of cores. The power controller may include a feedback control circuit to dynamically determine the hardware feedback information for at least one of the plurality of cores and inform the OS of an update to the hardware feedback information. Other embodiments are described and claimed.

公开(公告)号：US20220413859A1

公开(公告)日：2022-12-29

申请号：US17358082

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Kameswar Subramaniam ,  Jason W. Brandt ,  H. Peter Anvin ,  Christopher M. Russell ,  Gilbert Neiger

IPC: G06F9/30 ,  G06F9/455 ,  G06F9/48

Abstract: In one embodiment, a processor includes: a front end circuit to fetch and decode a read list instruction, the read list instruction to cause storage to a memory of a software-provided list of processor state information; and an execution circuit coupled to the front end circuit. The execution circuit, in response to the decoded read list instruction, is to read the processor state information stored in the processor and store each datum of the processor state information into an entry of a data table in the memory. Other embodiments are described and claimed.

公开(公告)号：US20220206791A1

公开(公告)日：2022-06-30

申请号：US17134100

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Wing Shek Wong ,  Kameswar Subramaniam ,  Eric Quintana

IPC: G06F9/22

Abstract: Systems, methods, and apparatuses relating to circuitry to implement a cross-lane packed data instruction on a partial (e.g., half) width processor with a minimal number of micro-operations are described. In one embodiment, a hardware processor core includes a decoder circuit to decode a single packed data instruction into only a first micro-operation and a second micro-operation, a packed data execution circuit to execute the first micro-operation and the second micro-operation, and a reservation station circuit coupled between the decoder circuit and the packed data execution circuit, the reservation station circuit comprising a first reservation station entry for the first micro-operation to store a first set of fields that indicate three or more input sources and a first destination, and a second reservation station entry for the second micro-operation to store a second set of fields to indicate three or more input sources and a second destination.

公开(公告)号：US12235791B2

公开(公告)日：2025-02-25

申请号：US17409090

申请日：2021-08-23

Applicant: Intel Corporation

Inventor： Kameswar Subramaniam ,  Christopher Russell

IPC: G06F9/38 ,  G06F9/32 ,  G06F15/78

Abstract: Methods and apparatus relating to loop driven region based frontend translation control for performant and secure data-space guided micro-sequencing are described. In an embodiment, Data-space Translation Logic (DTL) circuitry receives a static input and a dynamic input and generates one or more outputs based at least in part on the static input and the dynamic input. A frontend counter generates a count value for the dynamic input based at least in part on an incremented/decremented counter value and a next counter value from the DTL circuitry. The DTL circuitry is capable to receive a new dynamic input prior to consumption of the one or more outputs. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230057623A1

公开(公告)日：2023-02-23

申请号：US17409062

申请日：2021-08-23

Applicant: Intel Corporation

Inventor： Kameswar Subramaniam ,  Christopher Russell

IPC: G06F15/78 ,  G06F9/38

Abstract: Methods and apparatus relating to issue, execution, and backend driven frontend translation control for performant and secure data-space guided micro-sequencing are described. In an embodiment, Data-space Translation Logic (DTL) circuitry receives a static input and a dynamic input, and generates one or more outputs based at least in part on the static input and the dynamic input. The DTL circuitry generates the one or more outputs prior to commencement of speculation operations in a processor. Other embodiments are also disclosed and claimed.

公开(公告)号：US11354128B2

公开(公告)日：2022-06-07

申请号：US14639004

申请日：2015-03-04

Applicant: Intel Corporation

Inventor： Jason W. Brandt ,  Vedvyas Shanbhogue ,  Kameswar Subramaniam

IPC: G06F9/30

Abstract: In one embodiment, software executing on a data processing system that is capable of performing dynamic operational mode transitions can realize performance improvements by predicting transitions between modes and/or predicting aspects of a new operational mode. Such prediction can allow the processor to begin an early transition into the target mode. The mode transition prediction principles can be applied for various processor mode transitions including 64-bit to 32-bit mode transitions, interrupts, exceptions, traps, virtualization mode transfers, system management mode transfers, and/or secure execution mode transfers.

公开(公告)号：US20190205061A1

公开(公告)日：2019-07-04

申请号：US15858878

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Alexander Gendler ,  Efraim Rotem ,  Moshe Cohen ,  Asit K. Mallick ,  Jason W. Brandt ,  Kameswar Subramaniam ,  Nathan Fellman ,  Hisham Shafi

IPC: G06F3/06 ,  G06F9/30

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0673 ,  G06F9/30098 ,  G06F9/4406 ,  G06F9/45558 ,  G06F2009/45583

Abstract: Processor, method, and system for reducing latency in accessing remote registers is described herein. One embodiment of a processor includes one or more remote registers and remote register access circuitry. The remote register access circuitry is to detect a request from the requestor to access a first register of the one or more remote registers, access to the first register in accordance to the request without the requestor having to wait for completion of the access, and provide a notification accessible to the requestor upon completion of the access to the first register of the one or more remote registers.

公开(公告)号：US09612930B2

公开(公告)日：2017-04-04

申请号：US14737768

申请日：2015-06-12

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Eric Rasmussen ,  Deep K. Buch ,  Gordon McFadden ,  Kameswar Subramaniam ,  Amy L. Santoni ,  Willard M. Wiseman ,  Bret L. Toll

IPC: G06F11/00 ,  G06F11/263 ,  G06F11/22 ,  G06F11/14

CPC classification number: G06F11/2635 ,  G06F11/1417 ,  G06F11/1433 ,  G06F11/2242 ,  G06F11/2268 ,  G06F11/27

Abstract: In an embodiment, a processor includes at least one core, a power management unit having a first test register including a first field to store a test patch identifier associated with a test patch and a second field to store a test mode indicator to request a core functionality test, and a microcode storage to store microcode to be executed by the at least one core. Responsive to the test patch identifier, the microcode may access a firmware interface table and obtain the test patch from a non-volatile storage according to an address obtained from the firmware interface table. Other embodiments are described and claimed.

公开(公告)号：US20240330053A1

公开(公告)日：2024-10-03

申请号：US18194408

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Philip Abraham ,  Priya Autee ,  Stephen Van Doren ,  Yen-Cheng Liu ,  Rajesh Sankaran ,  Kameswar Subramaniam ,  Ritesh Parikh

IPC: G06F9/50 ,  G06F9/30

CPC classification number: G06F9/5016 ,  G06F9/3009 ,  G06F9/5044

Abstract: Techniques for region-aware memory bandwidth allocation control are described. In an embodiment, an apparatus includes a processing core and control circuitry. The processing core is to execute a plurality of threads. The control circuitry is to control use of memory bandwidth per memory region and per thread.