公开(公告)号：US20170250104A1

公开(公告)日：2017-08-31

申请号：US15523330

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Kanwal Jit SINGH ,  Alan M. MYERS

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/764 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/5329 ,  H01L29/78 ,  H01L2224/16225

Abstract: A method including forming a sacrificial material between metal lines of an integrated circuit structure; forming a mask on the sacrificial material; and after forming the mask, removing the sacrificial material to leave a void between the metal lines. An apparatus including an integrated circuit substrate; a first metallization level on the substrate; a second metallization;and a mask disposed between the first metallization level and the second metallization level, the mask including a dielectric material having a porosity select to allow mass transport therethrough, wherein each of the first metallization level and the second metallization level comprises a plurality of metal lines and a portion of adjacent metal lines of at least one of the first metallization level and the second metallization level are separated by voids.

公开(公告)号：US20190393157A1

公开(公告)日：2019-12-26

申请号：US16559086

申请日：2019-09-03

Applicant: Intel Corporation

Inventor： Boyan BOYANOV ,  Kanwal Jit SINGH

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/485 ,  H01L23/528 ,  H01L23/522

Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

公开(公告)号：US20180145035A1

公开(公告)日：2018-05-24

申请号：US15574816

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Kanwal Jit SINGH ,  Kevin LIN ,  Robert Lindsey BRISTOL

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/764 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/49827 ,  H01L23/5222 ,  H01L23/5226 ,  H01L29/0649 ,  H01L2221/1042 ,  H01L2221/1047

Abstract: Embodiments of the invention include interconnect layers with floating interconnect lines and methods of forming such interconnect layers. In an embodiment, a plurality of openings are formed in a first sacrificial material layer. Conductive vias and dielectric pillars may be formed in the openings. A second sacrificial material layer may then be formed over the pillars, the vias, and the first sacrificial material layer. In an embodiment, a permeable etchstop layer is formed over a top surface of the second sacrificial layer. Embodiments then include forming an interconnect line in the second sacrificial material layer. In an embodiment, the first and second sacrificial material layers are removed through the permeable etchstop layer after the interconnect line has been formed. According to an embodiment, the permeable etchstop layer may then be stuffed with a fill material in order to harden the permeable etchstop layer.

公开(公告)号：US20200321282A1

公开(公告)日：2020-10-08

申请号：US16908478

申请日：2020-06-22

Applicant: Intel Corporation

Inventor： Boyan BOYANOV ,  Kanwal Jit SINGH

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/485 ,  H01L23/528 ,  H01L23/522

Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

公开(公告)号：US20180086627A1

公开(公告)日：2018-03-29

申请号：US15573342

申请日：2015-06-22

Applicant: Intel Corporation

Inventor： Kevin LAI LIN ,  Chytra PAWASHE ,  Raseong KIM ,  Ian A. YOUNG ,  Kanwal Jit SINGH ,  Robert L. BRISTOL

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81B2207/015 ,  B81B2207/07 ,  B81B2207/092 ,  B81B2207/094 ,  B81B2207/095 ,  B81C1/00246 ,  B81C1/00301 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2203/0714 ,  B81C2203/0742 ,  B81C2203/0771 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829

Abstract: A conductive layer is deposited into a trench in a sacrificial layer on a substrate. An etch stop layer is deposited over the conductive layer. The sacrificial layer is removed to form a gap. In one embodiment, a beam is over a substrate. An interconnect is on the beam. An etch stop layer is over the beam. A gap is between the beam and the etch stop layer.

公开(公告)号：US20170330761A1

公开(公告)日：2017-11-16

申请号：US15528736

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Jasmeet S. CHAWLA ,  Ruth A. BRAIN ,  Richard E. SCHENKER ,  Kanwal Jit SINGH ,  Alan M. MEYERS

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/48 ,  H01L23/522

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/485 ,  H01L21/486 ,  H01L21/76804 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2224/16225

Abstract: Interconnect structures having alternating dielectric caps and an etchstop liner for semiconductor devices and methods for manufacturing such devices are described. According to an embodiment, an interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. The interconnect structure may also include one or more first interconnect lines in the ILD. A first dielectric cap may be positioned above a top surface of each of the first interconnect lines. Additional embodiments include one or more second interconnect lines in the ILD that are arranged in an alternating pattern with the first interconnect lines. A second dielectric cap may be formed above a top surface of each of the second interconnect lines. Embodiments may also include an etchstop liner that is formed over top surfaces of the first dielectric caps.

公开(公告)号：US20150270224A1

公开(公告)日：2015-09-24

申请号：US14675613

申请日：2015-03-31

Applicant: Intel Corporation

Inventor： Boyan BOYANOV ,  Kanwal Jit SINGH

IPC: H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

Abstract translation: 在衬底上的电介质层中的至少一个导电线凹入以形成沟道。 通道与导线自对准。 可以通过使用包含抑制剂的化学品将导电线蚀刻到预定深度来形成沟道，以提供独立于晶体取向的蚀刻均匀性。 用于防止电迁移的覆盖层沉积在通道中的凹进的导电线上。 通道被配置为在导电线的宽度内容纳覆盖层。