公开(公告)号：US20160180958A1

公开(公告)日：2016-06-23

申请号：US14579971

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： SHYAM SUNDER RAGHUNATHAN ,  IWEN CHAO ,  XIN GUO ,  PRANAV KALAVADE ,  KRISHNA K. PARAT ,  FENG ZHU

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/32 ,  G11C16/14

CPC classification number: G06F12/0246 ,  G06F11/1084 ,  G06F2212/7211 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/32 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/021 ,  G11C29/028

Abstract: Apparatus, systems, and methods to implement dynamic memory management in nonvolatile memory devices are described. In one example, a controller comprises logic to monitor at least one performance parameter of a nonvolatile memory, determine when the at least one performance parameter passes a threshold which indicates a degradation in performance for the nonvolatile memory, and in response to the at least one performance parameter passing the threshold, to modify at least one operational attribute of the nonvolatile memory. Other examples are also disclosed and claimed.

Abstract translation: 描述了在非易失性存储器件中实现动态存储器管理的装置，系统和方法。 在一个示例中，控制器包括用于监视非易失性存储器的至少一个性能参数的逻辑，确定何时至少一个性能参数通过指示非易失性存储器性能下降的阈值，以及响应于该至少一个 性能参数通过阈值，以修改非易失性存储器的至少一个操作属性。 还公开并要求保护其他实例。

公开(公告)号：US20170068482A1

公开(公告)日：2017-03-09

申请号：US14846102

申请日：2015-09-04

Applicant: INTEL CORPORATION

Inventor： ANAND S. RAMALINGAM ,  DALE J. JUENEMANN ,  PRANAV KALAVADE

IPC: G06F3/06 ,  G06F12/08 ,  G11C11/56

CPC classification number: G06F3/0647 ,  G06F3/061 ,  G06F3/0685 ,  G06F12/0804 ,  G06F12/0868 ,  G06F2212/1032 ,  G06F2212/214 ,  G06F2212/225 ,  G06F2212/261 ,  G06F2212/7203 ,  G11C11/5628 ,  G11C2211/5648

Abstract: Techniques are disclosed for programming memory devices such as solid-state drives. In an embodiment, a memory controller is configured to execute a programming sequence that interleaves coarse and fine tuning steps for neighboring word lines. In one example, three consecutive word lines are programmed in six steps. At step 1, word line n is coarse programmed to an intermediate voltage level; at step 2, word line n+1 is coarse programmed to an intermediate voltage level; at step 3, word line n is fine programmed to its target voltage level; at step 4, word line n+2 is coarse programmed to an intermediate voltage level; at step 5, word line n+1 is fine programmed to its target voltage level; at step 6, word line n+2 is fine programmed to its target voltage level. No reads are allowed until all cell levels are programmed. Phase change memory may be used as staging buffer.

Abstract translation: 公开了用于对诸如固态驱动器之类的存储器件进行编程的技术。 在一个实施例中，存储器控制器被配置为执行对相邻字线进行粗调和微调步骤的编程序列。 在一个示例中，三个连续的字线被编程为六个步骤。 在步骤1中，字线n被粗略地编程到中间电压电平; 在步骤2，字线n + 1被粗略地编程到中间电压电平; 在步骤3中，字线n被精细地编程到其目标电压电平; 在步骤4，字线n + 2被粗略地编程到中间电压电平; 在步骤5中，字线n + 1被精细地编程到其目标电压电平; 在步骤6，字线n + 2被精细地编程到其目标电压电平。 在所有单元格级别都被编程之前，不允许读取。 相变存储器可用作分段缓冲器。

公开(公告)号：US20200350028A1

公开(公告)日：2020-11-05

申请号：US16852162

申请日：2020-04-17

Applicant: Intel Corporation

Inventor： HAN ZHAO ,  PRANAV KALAVADE ,  KRISHNA K. PARAT

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/08 ,  G11C16/04

Abstract: Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates.

公开(公告)号：US20190043594A1

公开(公告)日：2019-02-07

申请号：US15831984

申请日：2017-12-05

Applicant: Intel Corporation

Inventor： HAN ZHAO ,  PRANAV KALAVADE ,  KRISHNA K. PARAT

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56

Abstract: Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates.

公开(公告)号：US20190043564A1

公开(公告)日：2019-02-07

申请号：US15845500

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： ALIASGAR S. MADRASWALA ,  BHARAT M. PATHAK ,  BINH N. NGO ,  NAVEEN VITTAL PRABHU ,  KARTHIKEYAN RAMAMURTHI ,  PRANAV KALAVADE

IPC: G11C11/56 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C11/5642 ,  G11C8/08 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C2211/5631

Abstract: A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.