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    TWO-STAGE CACHE PARTITIONING
    6.
    发明公开
    TWO-STAGE CACHE PARTITIONING 审中-公开

    公开(公告)号：US20230315632A1

    公开(公告)日：2023-10-05

    申请号：US17711471

    申请日：2022-04-01

    Applicant: Intel Corporation

    Inventor： Philip Abraham ,  Stephen Van Doren ,  Ritu Gupta ,  Andrew Herdrich

    IPC: G06F12/0811 ,  G06F12/0846 ,  G06F12/084

    CPC classification number: G06F12/0811 ,  G06F12/0846 ,  G06F12/084

    Abstract: Techniques and mechanisms to facilitate access to a cache based on a dual basis partition scheme. In an embodiment, a first one or more registers of a processor provide information which describes multiple set-wise partitions of a cache. A second one or more registers of the processor provides additional information which describes multiple way-wise partitions of the cache. A virtual cache is defined as that region of the cache which is both in a particular set-wise partition, and in a particular way-wise partition. In another embodiment, a cache agent of the processor performs operations, based on the set-wise partitioning and the way-wise partitioning, to determine a mapping of one address—which is provided in a memory access request, and which indicates a location in one virtual cache—to another address which indicates another location in a different virtual cache.

    Hardware lockstep checking within a fault detection interval in a system on chip
    8.
    发明授权
    Hardware lockstep checking within a fault detection interval in a system on chip 有权

    公开(公告)号：US10831628B2

    公开(公告)日：2020-11-10

    申请号：US16218078

    申请日：2018-12-12

    Applicant: Intel Corporation

    Inventor： Umberto Santoni ,  Rahul Pal ,  Philip Abraham ,  Mahesh Mamidipaka ,  C Santhosh

    IPC: G06F11/273 ,  G06F11/16 ,  G06F11/10

    Abstract: A method to check for redundancy in two or more data lines comprises receiving data on a first data line, computing a first cyclic redundancy check (CRC) value on the data of the first data line, performing an exclusive OR (XOR) function on the first CRC value with a stored memory value, and updating the stored memory value with a result of the XOR function, and repeating on additional data lines until a last line is processed such that an error is indicated if a final stored memory value is not zero. An apparatus to check that two cores are operating in lockstep comprises a first core comprising a first data checker, a second core comprising a second data checker, and a lockstep checker to compare an output of the first data checker with an output of the second data checker.

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