公开(公告)号：US11705453B2

公开(公告)日：2023-07-18

申请号：US16294380

申请日：2019-03-06

Applicant: Intel Corporation

Inventor： Sairam Subramanian ,  Walid M. Hafez ,  Sridhar Govindaraju ,  Kiran Chikkadi

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L23/528 ,  H01L21/768 ,  H01L21/308 ,  H01L23/00

CPC classification number: H01L27/0924 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/785

Abstract: Self-aligned gate endcap (SAGE) architectures having local interconnects, and methods of fabricating SAGE architectures having local interconnects, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin, and a second gate structure over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between and in contact with the first and second gate structures. A local gate interconnect is between the gate plug and the gate endcap isolation structure, the local gate interconnect in contact with the first and second gate structures.

公开(公告)号：US11688792B2

公开(公告)日：2023-06-27

申请号：US17526986

申请日：2021-11-15

Applicant: Intel Corporation

Inventor： Sairam Subramanian ,  Walid M. Hafez ,  Sridhar Govindaraju ,  Mark Liu ,  Szuya S. Liao ,  Chia-Hong Jan ,  Nick Lindert ,  Christopher Kenyon

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L29/66545 ,  H01L21/762 ,  H01L21/76895 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649

Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.

公开(公告)号：US11205708B2

公开(公告)日：2021-12-21

申请号：US15943556

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Sairam Subramanian ,  Walid M. Hafez ,  Sridhar Govindaraju ,  Mark Liu ,  Szuya S. Liao ,  Chia-Hong Jan ,  Nick Lindert ,  Christopher Kenyon

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/768

Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.

公开(公告)号：US09281401B2

公开(公告)日：2016-03-08

申请号：US14137909

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Sridhar Govindaraju ,  Matthew J. Prince

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L21/823437 ,  H01L21/31053 ,  H01L21/32115 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823475 ,  H01L23/49838 ,  H01L23/5329 ,  H01L23/535 ,  H01L24/16 ,  H01L27/0886 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785 ,  H01L2224/16227

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了减少晶体管栅极短缺陷的技术和配置。 在一个实施例中，一种方法包括形成多条线，其中多条线中的各条线包括栅电极材料，沉积电绝缘材料以填充各线之间的区域，然后在沉积电绝缘材料之后， 至少一个独立线路的部分，以将第一晶体管器件的栅电极材料与第二晶体管器件的栅电极材料隔离。 可以描述和/或要求保护其他实施例。

公开(公告)号：US11605632B2

公开(公告)日：2023-03-14

申请号：US17529029

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Sridhar Govindaraju ,  Mark Liu ,  Szuya S. Liao ,  Chia-Hong Jan ,  Nick Lindert ,  Christopher Kenyon ,  Sairam Subramanian

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L23/528

Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.

公开(公告)号：US11329138B2

公开(公告)日：2022-05-10

申请号：US15943552

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Sairam Subramanian ,  Christopher Kenyon ,  Sridhar Govindaraju ,  Chia-Hong Jan ,  Mark Liu ,  Szuya S. Liao ,  Walid M. Hafez

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088

Abstract: Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.

公开(公告)号：US12094780B2

公开(公告)日：2024-09-17

申请号：US18223981

申请日：2023-07-19

Applicant: Intel Corporation

Inventor： Sridhar Govindaraju ,  Matthew J. Prince

IPC: H01L21/8234 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L23/532 ,  H01L23/535 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  G06F30/39 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/02 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L21/823437 ,  H01L21/31053 ,  H01L21/32115 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823475 ,  H01L23/49838 ,  H01L23/5329 ,  H01L23/535 ,  H01L24/16 ,  H01L27/0886 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785 ,  G06F30/39 ,  H01L21/823871 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00 ,  H01L2924/0002

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

公开(公告)号：US11978776B2

公开(公告)日：2024-05-07

申请号：US16461071

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Ashutosh Sagar ,  Sridhar Govindaraju

IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/456 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2224/16502 ,  H01L2924/01322 ,  H01L2924/014

Abstract: An apparatus includes a non-planar semiconductor body; and a contact for the semiconductor body. The contact includes an epitaxial material that is formed on and contacts the semiconductor body. The contact includes a second material that is formed on and contacts the epitaxial material; and the second material at least partially conforms to an undercut of the epitaxial material.

公开(公告)号：US09704798B2

公开(公告)日：2017-07-11

申请号：US14137497

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Sridhar Govindaraju ,  Anindya Dasgupta ,  Rohit Grover

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485

CPC classification number: H01L23/5226 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer on a substrate; an opening in the dielectric layer, wherein the opening has opening sidewalls and exposes a conductive region of at least one of the substrate and an additional interconnect structure; a first atomic layer deposition (ALD) layer on the conductive region and the opening sidewalls; a second ALD layer on a portion of the first ALD layer, and a third ALD layer within the opening and on the first ALD layer. Other embodiments are described herein.

公开(公告)号：US20160141212A1

公开(公告)日：2016-05-19

申请号：US15008325

申请日：2016-01-27

Applicant: INTEL CORPORATION

Inventor： Sridhar Govindaraju ,  Matthew J. Prince

IPC: H01L21/8234 ,  H01L21/321 ,  H01L21/3105 ,  H01L27/088

CPC classification number: H01L21/823437 ,  H01L21/31053 ,  H01L21/32115 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823475 ,  H01L23/49838 ,  H01L23/5329 ,  H01L23/535 ,  H01L24/16 ,  H01L27/0886 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785 ,  H01L2224/16227

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.