中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

14 records (took 0.011 seconds)

    Integrated circuit with an increased signal bandwidth input/output (I/O) circuit
    3.
    发明授权
    Integrated circuit with an increased signal bandwidth input/output (I/O) circuit 有权

    公开(公告)号：US10110225B1

    公开(公告)日：2018-10-23

    申请号：US15341423

    申请日：2016-11-02

    Applicant: Intel Corporation

    Inventor： Ker Yon Lau ,  Tat Hin Tan ,  Choong Kit Wong

    IPC: H03K19/00 ,  H03K17/56

    Abstract: An input/output (I/O) circuit for an integrated circuit includes an input-output terminal, a termination circuit and an impedance compensation circuit. The termination circuit includes a node that is coupled to the input-output terminal. The termination circuit exhibits substantially constant first impedance below a first frequency of signals received at the input-output terminal. Furthermore, the termination circuit exhibits second impedance that is less than the first impedance when signals having a second frequency that is higher than the first frequency are received at the input-output terminal. The impedance compensation circuit is coupled to the input-output terminal. The impedance compensation circuit compensates for differences between the first and second impendences when the signal having the second frequency that is higher than the first frequency is received at the input-output terminal.

    MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING
    6.
    发明申请
    MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING 有权

    公开(公告)号：US20210320051A1

    公开(公告)日：2021-10-14

    申请号：US17155757

    申请日：2021-01-22

    Applicant: Intel Corporation

    Inventor： Bok Eng Cheah ,  Choong Kooi Chee ,  Jackson Chung Peng Kong ,  Wai Ling Lee ,  Tat Hin Tan

    IPC: H01L23/48 ,  H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L21/822

    Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

    MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING
    7.
    发明申请
    MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING 审中-公开

    公开(公告)号：US20200043831A1

    公开(公告)日：2020-02-06

    申请号：US16402482

    申请日：2019-05-03

    Applicant: Intel Corporation

    Inventor： Bok Eng Cheah ,  Choong Kooi Chee ,  Jackson Chung Peng Kong ,  Tat Hin Tan ,  Wai Ling Lee

    IPC: H01L23/48 ,  H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L21/822

    Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

    HIGH SPEED SENSE AMPLIFIER LATCH WITH LOW POWER RAIL-TO-RAIL INPUT COMMON MODE RANGE
    8.
    发明申请
    HIGH SPEED SENSE AMPLIFIER LATCH WITH LOW POWER RAIL-TO-RAIL INPUT COMMON MODE RANGE 审中-公开
    具有低功率轨至轨输入公共模式范围的高速感应放大器

    公开(公告)号：US20160380753A1

    公开(公告)日：2016-12-29

    申请号：US15262859

    申请日：2016-09-12

    Applicant: Intel Corporation

    Inventor： Pankaj Vinayak Dudulwar ,  Chenchu Punnarao Bandi ,  Lip Khoon Teh ,  Tat Hin Tan

    IPC: H04L7/00 ,  G11C7/10 ,  G11C7/06 ,  H03L7/081 ,  H04L27/00

    CPC classification number: H04L7/0037 ,  G11C7/062 ,  G11C7/065 ,  G11C7/08 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C11/165 ,  G11C11/4093 ,  G11C11/4096 ,  H03L7/0812 ,  H04L27/0002

    Abstract: Described is an apparatus which comprises: an input sensing stage for sensing an input signal relative to another signal; a decision making circuit, coupled to the input sensing stage, for determining whether the input signal is a logic low or a logic high; and a power management circuit, coupled to the input sensing stage and the decision making circuit, which is operable to monitor a state of the decision making circuit and to disable the input sensing stage according to the monitored state. Described is an apparatus which comprises: a decision making circuit integrated with an input sensing stage, wherein the decision making circuit is operable to pre-charge its internal nodes during a phase of the clock signal; and a latching circuit to latch an output of the decision making circuit.

    Abstract translation: 描述了一种装置，包括：用于感测相对于另一信号的输入信号的输入感测级; 耦合到输入感测级的判定电路，用于确定输入信号是逻辑低还是逻辑高; 以及耦合到输入感测级和决策电路的电源管理电路，其可操作以监视决策电路的状态并根据监视状态禁用输入感测级。 描述了一种装置，其包括：与输入感测级集成的决策电路，其中所述决策电路可操作以在所述时钟信号的相位期间对其内部节点进行预充电; 以及锁存电路，用于锁存所述决策电路的输出。

    High resolution and low power interpolator for delay chain
    10.
    发明授权
    High resolution and low power interpolator for delay chain 有权

    公开(公告)号：US10200046B1

    公开(公告)日：2019-02-05

    申请号：US15433853

    申请日：2017-02-15

    Applicant: Intel Corporation

    Inventor： Chee Seng Leong ,  Tat Hin Tan

    IPC: H03L7/06 ,  H03L7/081 ,  H03K5/135 ,  H03K5/06 ,  H03K5/00

    Abstract: A delay-locked loop includes multiple inverters coupled together, wherein the inverters receive an input clock signal and output a first clock signal and a second clock signal. The input clock signal passes through a first set of inverters having a first number of inverters to generate the first clock signal. The input clock signal also passes through a second set of inverters having a second number of inverters one inverter greater than the first number of inverters to generate the second clock signal. The delay-locked loop also includes a polarity matching block that receives the first clock signal and the second clock signal and changes polarity of one of the first clock signal and the second clock signal.

Patent Agency Ranking