公开(公告)号：US12048165B2

公开(公告)日：2024-07-23

申请号：US16914140

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Sou-Chi Chang ,  Shriram Shivaraman ,  I-Cheng Tung ,  Tobias Brown-Heft ,  Devin R. Merrill ,  Che-Yun Lin ,  Seung Hoon Sung ,  Jack Kavalieros ,  Uygar Avci ,  Matthew V. Metz

IPC: H10B53/00 ,  G11C11/22 ,  H01G4/008 ,  H01L27/08 ,  H01L49/02 ,  H10B53/10

CPC classification number: H10B53/00 ,  G11C11/221 ,  H01G4/008 ,  H01L27/0805 ,  H01L28/65 ,  H10B53/10

Abstract: An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.

公开(公告)号：US12080781B2

公开(公告)日：2024-09-03

申请号：US17129867

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Sarah Atanasov ,  Abhishek A. Sharma ,  Bernhard Sell ,  Chieh-Jen Ku ,  Elliot N. Tan ,  Hui Jae Yoo ,  Travis W. Lajoie ,  Van H. Le ,  Pei-Hua Wang ,  Jason Peck ,  Tobias Brown-Heft

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L27/0924

Abstract: Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure. Other embodiments may be described and claimed.

公开(公告)号：US20240373644A1

公开(公告)日：2024-11-07

申请号：US18778857

申请日：2024-07-19

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Sou-Chi Chang ,  Shriram Shivaraman ,  I-Cheng Tung ,  Tobias Brown-Heft ,  Devin R. Merrill ,  Che-Yun Lin ,  Seung Hoon Sung ,  Jack Kavalieros ,  Uygar Avci ,  Matthew V. Metz

IPC: H10B53/00 ,  G11C11/22 ,  H01G4/008 ,  H01L27/08 ,  H10B53/10

Abstract: An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.

公开(公告)号：US20210408018A1

公开(公告)日：2021-12-30

申请号：US16914140

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Sou-Chi Chang ,  Shriram Shivaraman ,  I-Cheng Tung ,  Tobias Brown-Heft ,  Devin R. Merrill ,  Che-Yun Lin ,  Seung Hoon Sung ,  Jack Kavalieros ,  Uygar Avci ,  Matthew V. Metz

IPC: H01L27/11502 ,  H01L49/02 ,  H01L27/08 ,  H01G4/008 ,  G11C11/22

Abstract: An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.

公开(公告)号：US12183739B2

公开(公告)日：2024-12-31

申请号：US17127280

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Nicole Thomas ,  Eric Mattson ,  Sudarat Lee ,  Scott B. Clendenning ,  Tobias Brown-Heft ,  I-Cheng Tung ,  Thoe Michaelos ,  Gilbert Dewey ,  Charles Kuo ,  Matthew Metz ,  Marko Radosavljevic ,  Charles Mokhtarzadeh

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (Vt). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vt within the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.

公开(公告)号：US20220199620A1

公开(公告)日：2022-06-23

申请号：US17127280

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Nicole Thomas ,  Eric Mattson ,  Sudarat Lee ,  Scott B. Clendenning ,  Tobias Brown-Heft ,  I-Cheng Tung ,  Thoe Michaelos ,  Gilbert Dewey ,  Charles Kuo ,  Matthew Metz ,  Marko Radosavljevic ,  Charles Mokhtarzadeh

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

Abstract: Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (Vt). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vt within the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.

公开(公告)号：US20220199619A1

公开(公告)日：2022-06-23

申请号：US17133208

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Ashish Verma Penumatcha ,  Seung Hoon Sung ,  Jack Kavalieros ,  Uygar Avci ,  Tristan Tronic ,  Shriram Shivaraman ,  Devin Merrill ,  Tobias Brown-Heft ,  Kirby Maxey ,  Matthew Metz ,  Ian Young

IPC: H01L27/092 ,  H01L27/22 ,  H01L27/24 ,  H01L43/02 ,  H01L43/08 ,  H01L45/00 ,  H01L43/12

Abstract: A complementary metal oxide semiconductor (CMOS) transistor includes a first transistor with a first gate dielectric layer above a first channel, where the first gate dielectric layer includes Hf1-xZxO2, where 0.33