公开(公告)号：US12057402B2

公开(公告)日：2024-08-06

申请号：US17025166

申请日：2020-09-18

申请人： Intel Corporation

发明人： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan ,  Feras Eid ,  Randy B. Osborne ,  Van H. Le

IPC分类号： H01L23/538 ,  H01L23/49 ,  H01L25/065

CPC分类号： H01L23/5384 ,  H01L23/49 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/0657

摘要： Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include an interposer, including an organic dielectric material, and a microelectronic component coupled to the interposer by direct bonding.

公开(公告)号：US20230369503A1

公开(公告)日：2023-11-16

申请号：US17742664

申请日：2022-05-12

申请人： Intel Corporation

发明人： Cheng Tan ,  Van H. Le ,  Akash Garg ,  Shokir A. Pardaev ,  Timothy Jen ,  Abhishek Anil Sharma ,  Thiruselvam Ponnusamy ,  Moira C. Vyner ,  Caleb Barrett ,  Forough Mahmoudabadi ,  Albert B. Chen ,  Travis W. Lajoie ,  Christopher M. Pelto

IPC分类号： H01L29/786 ,  H01L23/522 ,  H01L27/108 ,  H01L29/417

CPC分类号： H01L29/78618 ,  H01L23/5226 ,  H01L27/10805 ,  H01L29/7869 ,  H01L29/41733

摘要： Techniques are provided for making asymmetric contacts to improve the performance of thin film transistors (TFT) structures. The asymmetry may be with respect to the area of contact interface with the semiconductor region and/or the depth to which the contacts extend into the semiconductor region. According to some embodiments, the TFT structures are used in memory structures arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include asymmetric contacts, such as two contacts that each have a different contact area to a semiconductor region, and/or that extend to different depths within the semiconductor region. The degree of asymmetry may be tuned during fabrication to modulate certain transistor parameters such as, for example, leakage, capacitance, gate control, channel length, or contact resistance.

公开(公告)号：US20230369501A1

公开(公告)日：2023-11-16

申请号：US17742631

申请日：2022-05-12

申请人： Intel Corporation

发明人： Cheng Tan ,  Yu-Wen Huang ,  Hui-Min Chuang ,  Xiaojun Weng ,  Nikhil J. Mehta ,  Allen B. Gardiner ,  Shu Zhou ,  Timothy Jen ,  Abhishek Anil Sharma ,  Van H. Le ,  Travis W. Lajoie ,  Bernhard Sell

IPC分类号： H01L29/786 ,  H01L27/108

CPC分类号： H01L29/78606 ,  H01L27/10814 ,  H01L29/78696 ,  H01L27/10873

摘要： Techniques are provided herein for forming transistor devices with reduced parasitic capacitance, such as transistors used in a memory structure. In an example, a given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT), and the storage device may include a capacitor. Any of the given TFTs may include a dielectric liner extending along sidewalls of the TFT. The TFT includes a recess (e.g., a dimple) that extends laterally inwards toward a midpoint of a semiconductor region of the TFT. The dielectric liner thus also pinches or otherwise extends inward. This pinched-in dielectric liner may reduce parasitic capacitance between the contacts of the TFT and the gate electrode of the TFT. The pinched-in dielectric liner may also protect the contacts from forming too deep into the semiconductor region.

公开(公告)号：US11777013B2

公开(公告)日：2023-10-03

申请号：US16457626

申请日：2019-06-28

申请人： Intel Corporation

发明人： Abhishek Sharma ,  Willy Rachmady ,  Van H. Le ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Matthew Metz

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L29/45 ,  H01L29/786 ,  H01L29/417

CPC分类号： H01L29/66742 ,  H01L21/0262 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/78696

摘要： Embodiments herein describe techniques for a three dimensional transistor above a substrate. A three dimensional transistor includes a channel structure, where the channel structure includes a channel material and has a source area, a drain area, and a channel area between the source area and the drain area. A source electrode is coupled to the source area, a drain electrode is coupled to the drain area, and a gate electrode is around the channel area. An electrode selected from the source electrode, the drain electrode, or the gate electrode is in contact with the channel material on a sidewall of an opening in an inter-level dielectric layer or a surface of the electrode. The electrode is further in contact with the channel structure including the source area, the drain area, or the channel area. Other embodiments may be described and/or claimed.

公开(公告)号：US11700776B2

公开(公告)日：2023-07-11

申请号：US17592724

申请日：2022-02-04

申请人： Intel Corporation

发明人： Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Zachary R. Yoscovits ,  James S. Clarke ,  Van H. Le

IPC分类号： H10N60/10 ,  G06N10/00 ,  H10N60/12 ,  H10N60/80 ,  H10N60/01

CPC分类号： H10N60/128 ,  G06N10/00 ,  H10N60/0912 ,  H10N60/12 ,  H10N60/805

摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.

公开(公告)号：US11699681B2

公开(公告)日：2023-07-11

申请号：US16727779

申请日：2019-12-26

申请人： Intel Corporation

发明人： Abhishek Sharma ,  Hui Jae Yoo ,  Van H. Le ,  Huseyin Ekin Sumbul ,  Phil Knag ,  Gregory K. Chen ,  Ram Krishnamurthy

IPC分类号： H01L25/065 ,  G11C11/407

CPC分类号： H01L25/0657 ,  G11C11/407 ,  H01L2224/32145 ,  H01L2224/32225

摘要： An apparatus is formed. The apparatus includes a stack of semiconductor chips. The stack of semiconductor chips includes a logic chip and a memory stack, wherein, the logic chip includes at least one of a GPU and CPU. The apparatus also includes a semiconductor chip substrate. The stack of semiconductor chips are mounted on the semiconductor chip substrate. At least one other logic chip is mounted on the semiconductor chip substrate. The semiconductor chip substrate includes wiring to interconnect the stack of semiconductor chips to the at least one other logic chip.

公开(公告)号：US11652047B2

公开(公告)日：2023-05-16

申请号：US16457641

申请日：2019-06-28

申请人： Intel Corporation

发明人： Travis W. Lajoie ,  Abhishek A. Sharma ,  Van H. Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani ,  Gregory George ,  Akash Garg ,  Julie Rollins ,  Allen B. Gardiner ,  Shem Ogadhoh ,  Juan G. Alzate Vinasco ,  Umut Arslan ,  Fatih Hamzaoglu ,  Nikhil Mehta ,  Ting Chen ,  Vinaykumar V. Hadagali

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L27/108

CPC分类号： H01L23/528 ,  H01L23/5226 ,  H01L27/1085 ,  H01L27/10805 ,  H01L27/10873

摘要： Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.

公开(公告)号：US20230057464A1

公开(公告)日：2023-02-23

申请号：US17981561

申请日：2022-11-07

申请人： Intel Corporation

发明人： Sean T. Ma ,  Aaron D. Lilak ,  Abhishek A. Sharma ,  Van H. Le ,  Seung Hoon Sung ,  Gilbert W. Dewey ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Tahir Ghani

IPC分类号： H01L27/108 ,  H01L21/822 ,  H01L23/528 ,  H01L49/02 ,  H01L29/06

摘要： Disclosed herein are memory cells and memory arrays, as well as related methods and devices. For example, in some embodiments, a memory device may include: a support having a surface; and a three-dimensional array of memory cells on the surface of the support, wherein individual memory cells include a transistor and a capacitor, and a channel of the transistor in an individual memory cell is oriented parallel to the surface.

公开(公告)号：US20230022167A1

公开(公告)日：2023-01-26

申请号：US17382575

申请日：2021-07-22

申请人： Intel Corporation

发明人： Prashant Majhi ,  Brian S. Doyle ,  Abhishek A. Sharma ,  Van H. Le

IPC分类号： H01L25/10 ,  H01L29/786 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

摘要： Integrated circuit (IC) assemblies with stacked compute logic and memory dies, and associated systems and methods, are disclosed. One example IC assembly includes a compute logic die and a stack of memory dies provided above and coupled to the compute logic die, where one or more of the memory dies closest to the compute logic die include memory cells with transistors that are thin-film transistors (TFTs), while one or more of the memory dies further away from the compute logic die include memory cells with non-TFT transistors. Another example IC assembly includes a similar stack of compute logic die and memory dies where one or more of the memory dies closest to the compute logic die include static random-access memory (SRAM) cells, while one or more of the memory dies further away from the compute logic die include memory cells of other memory types.

公开(公告)号：US11527656B2

公开(公告)日：2022-12-13

申请号：US16141408

申请日：2018-09-25

申请人： Intel Corporation

发明人： Van H. Le ,  Tahir Ghani ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Matthew Metz ,  Miriam Reshotko ,  Benjamin Chu-Kung ,  Shriram Shivaraman ,  Abhishek Sharma ,  Nazila Haratipour

IPC分类号： H01L29/786 ,  H01L29/423 ,  H01L27/24 ,  H01L29/66 ,  H01L27/108 ,  H01L29/45

摘要： Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a source electrode or a drain electrode is above or below the channel layer, separated from the gate electrode, and in contact with a portion of the channel layer. Other embodiments may be described and/or claimed.