公开(公告)号：US09196475B2

公开(公告)日：2015-11-24

申请号：US14253906

申请日：2014-04-16

Applicant: GLOBALFOUNDRIES, Inc. ,  Intermolecular, Inc.

Inventor： Bongki Lee ,  Paul Besser ,  Kevin Kashefi ,  Olov Karlsson ,  Ashish Bodke ,  Ratsamee Limdulpaiboon ,  Divya Pisharoty ,  Nobi Fuchigami

IPC: H01L23/48 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L21/02181 ,  H01L21/02164 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3105 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，制造集成电路的方法包括在FET区域中形成电介质氧化物材料的中间层并覆盖在半导体衬底上。 沉积在中间层上方的高K电介质层。 氟被并入到中间层和/或高K电介质层中。

公开(公告)号：US20150118828A1

公开(公告)日：2015-04-30

申请号：US14068906

申请日：2013-10-31

Applicant: Intermolecular Inc.

Inventor： Frank Greer ,  Amol Joshi ,  Kevin Kashefi ,  Albert Sanghyup Lee ,  Abhijit Pethe ,  J Watanabe

IPC: H01L21/28 ,  H01L21/02

CPC classification number: H01L21/28158 ,  C23C16/0218 ,  C23C16/45525 ,  H01L21/02175 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/28238

Abstract: Native oxide growth on germanium, silicon germanium, and InGaAs undesirably affects CET (capacitive equivalent thickness) and EOT (effective oxide thickness) of high-k and low-k metal-oxide layers formed on these semiconductors. Even if pre-existing native oxide is initially removed from the bare semiconductor surface, some metal oxide layers are oxygen-permeable in thicknesses below about 25 Å thick. Oxygen-containing species used in the metal-oxide deposition process may diffuse through these permeable layers, react with the underlying semiconductor, and re-grow the native oxide. To eliminate or mitigate this re-growth, the substrate is exposed to a gas or plasma reductant (e.g., containing hydrogen). The reductant diffuses through the permeable layers to react with the re-grown native oxide, detaching the oxygen and leaving the un-oxidized semiconductor. The reduction product(s) resulting from the reaction may then be removed from the substrate (e.g., driven off by heat).

Abstract translation: 在锗，硅锗和InGaAs上的天然氧化物生长不利地影响在这些半导体上形成的高k和低k金属氧化物层的CET（电容等效厚度）和EOT（有效氧化物厚度）。 即使预先存在的原生氧化物最初从裸露的半导体表面去除，一些金属氧化物层的厚度可以在大约25埃的厚度下透氧。 在金属氧化物沉积工艺中使用的含氧物质可以扩散通过这些可渗透层，与下面的半导体反应，并重新生长天然氧化物。 为了消除或减轻这种再生长，将基底暴露于气体或等离子体还原剂（例如含有氢气）中。 还原剂通过可渗透层扩散以与再生的天然氧化物反应，分离氧并留下未氧化的半导体。 然后可以从反应物中除去由反应产生的还原产物（例如，通过加热驱除）。

公开(公告)号：US09224594B2

公开(公告)日：2015-12-29

申请号：US14083124

申请日：2013-11-18

Applicant: Intermolecular Inc.

Inventor： Kevin Kashefi ,  Frank Greer

IPC: H01L21/314 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L21/02304 ,  H01L21/02046 ,  H01L21/02181 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/0228 ,  H01L21/02301 ,  H01L21/28194 ,  H01L29/517

Abstract: Methods and apparatus for processing using a plasma source for the treatment of semiconductor surfaces are disclosed. The apparatus includes an outer vacuum chamber enclosing a substrate support, a plasma source (either a direct plasma or a remote plasma), and an optional showerhead. Other gas distribution and gas dispersal hardware may also be used. The plasma source may be used to generate activated species operable to alter the surface of the semiconductor materials. Further, the plasma source may be used to generate activated species operable to enhance the nucleation of deposition precursors on the semiconductor surface.

Abstract translation: 公开了使用等离子体源处理半导体表面的方法和装置。 该装置包括封闭衬底支撑件的外部真空室，等离子体源（直接等离子体或远程等离子体）和可选的喷头。 也可以使用其他气体分配和气体分散硬件。 等离子体源可用于产生可操作以改变半导体材料的表面的活化物质。 此外，等离子体源可以用于产生可操作以增强半导体表面上的沉积前体的成核的活化物质。

公开(公告)号：US20170062522A1

公开(公告)日：2017-03-02

申请号：US15235992

申请日：2016-08-12

Applicant: Intermolecular, Inc.

Inventor： Salil Mujumdar ,  Abhijit Pethe ,  Ashish Bodke ,  Kevin Kashefi

IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

CPC classification number: H01L27/24 ,  G11C11/1659 ,  G11C13/003 ,  G11C2213/15 ,  G11C2213/52 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/148

Abstract: Provided are selector elements having snapback characteristics and non-volatile memory cells comprising such selector elements. To achieve its snapback characteristic, a selector element may include a dielectric layer comprising an alloy of two or more materials. In the same or other embodiments, the selector element may include a doped electrode, such carbon electrodes doped with silicon, germanium, and/or selenium. Concentrations of different materials forming an alloy may vary throughout the thickness of the dielectric layer. For example, the concentration of the first one alloy material may be higher in the center of the dielectric layer than near the interfaces of the dielectric layer with the electrodes. Some examples of this alloy material include germanium, indium, and aluminum. Examples of other materials in the same alloy include silicon, gallium, arsenic, and antimony. In some embodiments, the alloy is formed by three or more elements, such as indium gallium arsenic.

Abstract translation: 提供具有快速恢复特性的选择器元件和包括这种选择器元件的非易失性存储单元。 为了实现其回跳特性，选择器元件可以包括包含两种或更多种材料的合金的电介质层。 在相同或其它实施例中，选择器元件可以包括掺杂电极，掺杂有硅，锗和/或硒的碳电极。 形成合金的不同材料的浓度可以在电介质层的整个厚度上变化。 例如，第一种合金材料的浓度在电介质层的中心处可以比在具有电极的介电层的界面附近更高。 该合金材料的一些实例包括锗，铟和铝。 相同合金中的其它材料的实例包括硅，镓，砷和锑。 在一些实施例中，合金由三种或更多种元素形成，例如铟镓砷。

公开(公告)号：US20160149129A1

公开(公告)日：2016-05-26

申请号：US14553632

申请日：2014-11-25

Applicant: Intermolecular, Inc.

Inventor： Ashish Bodke ,  Mark Clark ,  Kevin Kashefi ,  Prashant B. Phatak ,  Dipankar Pramanik

IPC: H01L45/00

CPC classification number: H01L45/145 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253

Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The metal layer of the selector element can include conductive materials such as metal silicides, and metal silicon nitrides. Conductive materials of the MSM may include tantalum silicide, tantalum silicon nitride, titanium silicide, titanium silicon nitride, or combinations thereof.

Abstract translation: 公开了适用于非易失性存储器件应用的选择元件。 选择器元件在低电压下可以具有低泄漏电流，以减少非选定器件的潜行电流路径，以及在较高电压下更高的漏电流，以最大限度地减少器件切换期间的电压降。 选择器元件可以基于多层膜堆叠（例如金属 - 半导体 - 金属（MSM）堆叠）。 选择元件的金属层可以包括诸如金属硅化物的导电材料和金属硅氮化物。 MSM的导电材料可以包括硅化钽，氮化钽，硅化钛，氮化钛或其组合。

公开(公告)号：US20160149128A1

公开(公告)日：2016-05-26

申请号：US14553443

申请日：2014-11-25

Applicant: Intermolecular, Inc.

Inventor： Ashish Bodke ,  Mark Clark ,  Kevin Kashefi ,  Prashant B. Phatak

IPC: H01L45/00

CPC classification number: H01L45/1286 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146 ,  H01L45/149

Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). A structure including diamond-like carbon (DLC) can be used to surround the semiconductor layer of the MSM stack. The high thermal conductivity of the DLC structure may serve to remove heat from the selector device while higher currents are flowing through the selector element. This may lead to improved reliability and improved endurance.

Abstract translation: 公开了适用于非易失性存储器件应用的选择元件。 选择器元件在低电压下可以具有低泄漏电流，以减少非选定器件的潜行电流路径，以及在较高电压下更高的漏电流，以最大限度地减少器件切换期间的电压降。 选择器元件可以基于多层膜堆叠（例如金属 - 半导体 - 金属（MSM）堆叠）。 可以使用包括类金刚石碳（DLC）的结构来围绕MSM堆叠的半导体层。 DLC结构的高热导率可用于在较高的电流流过选择器元件时从选择器装置移除热量。 这可能导致改进的可靠性和耐久性。

公开(公告)号：US20160148976A1

公开(公告)日：2016-05-26

申请号：US14554388

申请日：2014-11-26

Applicant: Intermolecular, Inc.

Inventor： Ashish Bodke ,  Mark Clark ,  Kevin Kashefi ,  Prashant B. Phatak ,  Dipankar Pramanik

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2409 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/145 ,  H01L45/149

Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on a silicon semiconductor layer doped with both carbon and nitrogen. The metal layer of the selector element can include conductive materials such as carbon, tungsten, titanium nitride, or combinations thereof.

Abstract translation: 公开了适用于非易失性存储器件应用的选择元件。 选择器元件在低电压下可以具有低泄漏电流，以减少非选定器件的潜行电流路径，以及在较高电压下更高的漏电流，以最大限度地减少器件切换期间的电压降。 选择器元件可以基于掺杂有碳和氮的硅半导体层。 选择元件的金属层可以包括诸如碳，钨，氮化钛或其组合的导电材料。

公开(公告)号：US20160141335A1

公开(公告)日：2016-05-19

申请号：US14546678

申请日：2014-11-18

Applicant: Intermolecular, Inc.

Inventor： Ashish Bodke ,  Mark Clark ,  Kevin Kashefi ,  Prashant B. Phatak

IPC: H01L27/24 ,  H01L29/165 ,  H01L29/06 ,  H01L29/45 ,  H01L29/417 ,  H01L29/16 ,  H01L29/861

CPC classification number: H01L27/2409 ,  G11C11/1659 ,  G11C13/003 ,  G11C2213/76 ,  H01L27/222 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233

Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a trilayer stack of diamond like carbon/silicon/diamond like carbon. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or a combination thereof.

Abstract translation: 公开了适用于非易失性存储器件应用的选择元件。 选择器元件在低电压下可以具有低泄漏电流，以减少非选定器件的潜行电流路径，以及在较高电压下更高的漏电流，以最大限度地减少器件切换期间的电压降。 选择器元件可以基于多层膜堆叠（例如金属 - 半导体 - 金属（MSM）堆叠）。 选择器元件的半导体层可以包括诸如碳/硅/金刚石的类似碳的类金刚石叠层。 MSM的导电材料可以包括钨，氮化钛，碳或它们的组合。

公开(公告)号：US09246092B1

公开(公告)日：2016-01-26

申请号：US14554458

申请日：2014-11-26

Applicant: Intermolecular, Inc.

Inventor： Ashish Bodke ,  Mark Clark ,  Kevin Kashefi ,  Prashant B. Phatak ,  Dipankar Pramanik

IPC: H01L27/148 ,  H01L29/768 ,  H01L45/00

CPC classification number: H01L45/00 ,  H01L27/2409 ,  H01L27/2418 ,  H01L45/08 ,  H01L45/1233

Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can include insulator layers between the semiconductor layer and the metal layers to lower the leakage current of the device. The metal layers of the selector element can include conductive materials such as tungsten, titanium nitride, or combinations thereof.

Abstract translation: 公开了适用于非易失性存储器件应用的选择元件。 选择器元件在低电压下可以具有低泄漏电流，以减少非选定器件的潜行电流路径，以及在较高电压下更高的漏电流，以最大限度地减少器件切换期间的电压降。 选择器元件可以包括半导体层和金属层之间的绝缘体层，以降低器件的漏电流。 选择元件的金属层可以包括诸如钨，氮化钛或其组合的导电材料。

公开(公告)号：US09312137B2

公开(公告)日：2016-04-12

申请号：US14068906

申请日：2013-10-31

Applicant: Intermolecular Inc.

Inventor： Frank Greer ,  Amol Joshi ,  Kevin Kashefi ,  Albert Sanghyup Lee ,  Abhijit Pethe ,  J Watanabe

IPC: H01L21/00 ,  H01L21/28 ,  H01L21/02 ,  C23C16/02 ,  C23C16/455

CPC classification number: H01L21/28158 ,  C23C16/0218 ,  C23C16/45525 ,  H01L21/02175 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/28238

Abstract: Native oxide growth on germanium, silicon germanium, and InGaAs undesirably affects CET (capacitive equivalent thickness) and EOT (effective oxide thickness) of high-k and low-k metal-oxide layers formed on these semiconductors. Even if pre-existing native oxide is initially removed from the bare semiconductor surface, some metal oxide layers are oxygen-permeable in thicknesses below about 25 Å thick. Oxygen-containing species used in the metal-oxide deposition process may diffuse through these permeable layers, react with the underlying semiconductor, and re-grow the native oxide. To eliminate or mitigate this re-growth, the substrate is exposed to a gas or plasma reductant (e.g., containing hydrogen). The reductant diffuses through the permeable layers to react with the re-grown native oxide, detaching the oxygen and leaving the un-oxidized semiconductor. The reduction product(s) resulting from the reaction may then be removed from the substrate (e.g., driven off by heat).