利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

12 条记录 (耗时 0.017 秒)

    Method and apparatus for forming angled vias in an integrated circuit package substrate
    1.
    发明申请
    Method and apparatus for forming angled vias in an integrated circuit package substrate 审中-公开
    用于在集成电路封装衬底中形成倾斜通孔的方法和装置

    公开(公告)号：US20060131283A1

    公开(公告)日：2006-06-22

    申请号：US11016440

    申请日：2004-12-17

    申请人： Jeffrey Hall ,  Yogendra Ranade ,  Sarathy Rajagopalan

    发明人： Jeffrey Hall ,  Yogendra Ranade ,  Sarathy Rajagopalan

    IPC分类号： B23K26/38

    CPC分类号： H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/48227 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/0047 ,  H05K3/42 ,  H05K2201/09836 ,  Y10T408/86

    摘要： A method and apparatus for making angled vias in an integrated circuit package substrate includes providing an integrated circuit package substrate having an upper surface and a lower surface. A first position is selected for a first via opening on the upper surface of the package substrate, and a second position is selected for a second via opening on the lower surface of the package substrate. A selected non-vertical angle is determined for forming an angled via through the first position and the second position. The angled via is formed through the first position and the second position at the selected non-vertical angle.

    摘要翻译： 一种用于在集成电路封装衬底中形成倾斜通孔的方法和装置包括提供具有上表面和下表面的集成电路封装衬底。 对于封装基板的上表面上的第一通孔，选择第一位置，并且在封装基板的下表面上选择用于第二通孔的第二位置。 确定所选择的非垂直角以形成通过第一位置和第二位置的成角度的通孔。 成角度的通孔以选定的非垂直角通过第一位置和第二位置形成。

    Method of planarizing die solder balls by employing a die's weight
    4.
    发明授权
    Method of planarizing die solder balls by employing a die's weight 有权
    通过使用模具的重量来平坦化模具焊球的方法

    公开(公告)号：US06465338B1

    公开(公告)日：2002-10-15

    申请号：US09612867

    申请日：2000-07-10

    申请人： Sarathy Rajagopalan ,  Kishor V. Desai ,  Zafer S. Kutlu

    发明人： Sarathy Rajagopalan ,  Kishor V. Desai ,  Zafer S. Kutlu

    IPC分类号： H01L2144

    CPC分类号： H05K3/3457 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H05K2201/10734 ,  H05K2203/0278 ,  H05K2203/159 ,  H01L2224/0401

    摘要： Disclosed is a method of planarizing an array of plastically-deformable electrical contacts on an integrated circuit. An integrated circuit is placed on a plate with an array of plastically-deformable electrical contacts substantially parallel to and facing the plate, thereby creating an assembly. The integrated circuit is placed above the plate such that the weight of the integrated circuit bears down on the array of plastically-deformable electrical contacts. The assembly is then heated sufficiently to cause individual ones of the plastically-deformable electrical contacts to locally soften but not to cause said individual ones of the electrical contacts to liquefy throughout their volumes. The weight of the integrated circuit applies a force to the softened plastically-deformable electrical contacts, thereby resulting in their planarization.

    摘要翻译： 公开了一种在集成电路上平坦化可塑性变形的电触头阵列的方法。 集成电路放置在具有基本上平行于并面向板的可塑性变形的电触头阵列的板上，从而形成组件。 集成电路放置在板上方，使得集成电路的重量落在可塑性变形的电触头阵列上。 然后将组件充分加热以使得可塑性变形的电接触件中的单独一个局部软化，但不会使所述单个电触点在其整个体积中液化。 集成电路的重量对软化的可塑性变形的电触点施加力，从而导致其平坦化。

    Integrated circuit package design
    5.
    发明授权
    Integrated circuit package design 有权
    集成电路封装设计

    公开(公告)号：US07352062B2

    公开(公告)日：2008-04-01

    申请号：US10979491

    申请日：2004-11-02

    申请人： Mukul A. Joshi ,  Mohan R. Nagar ,  Sarathy Rajagopalan

    发明人： Mukul A. Joshi ,  Mohan R. Nagar ,  Sarathy Rajagopalan

    IPC分类号： H01L23/10 ,  H01L23/34

    CPC分类号： H01L23/36 ,  H01L23/42 ,  H01L23/4334 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/16152 ,  H01L2924/3025 ,  H01L2224/0401

    摘要： A packaged integrated circuit including a package substrate having electrical contacts for receiving an integrated circuit. The integrated circuit is electrically connected to the electrical contacts of the package substrate. A stiffener is mounted to the package substrate, where the stiffener has a non-orthogonal cut out in which the integrated circuit is disposed. The edges of the cut out are disposed at no greater a distance from the corners of the integrated circuit than they are from the sides of the integrated circuit.

    摘要翻译： 一种封装集成电路，包括具有用于接收集成电路的电触点的封装基板。 集成电路电连接到封装衬底的电触头。 加强件安装到封装基板上，其中加强件具有非正交切口，集成电路设置在其中。 切出的边缘设置在与集成电路的侧面不同于集成电路的角落的距离以上。

    Method and apparatus for thermal profiling of flip-chip packages
    6.
    发明授权
    Method and apparatus for thermal profiling of flip-chip packages 有权
    倒装芯片封装的热分析方法和装置

    公开(公告)号：US06962437B1

    公开(公告)日：2005-11-08

    申请号：US09465131

    申请日：1999-12-16

    申请人： Sarathy Rajagopalan ,  Minh Vuong

    发明人： Sarathy Rajagopalan ,  Minh Vuong

    IPC分类号： G01K7/00 ,  G01K7/02

    CPC分类号： G01K7/02

    摘要： A thermal measurement device for obtaining accurate thermal profiles during flip-chip semiconductor packaging and methodologies for making such devices is disclosed. Particularly, a measurement device comprised of a thermocouple sandwiched between a semiconductor packaging substrate and a semiconductor die. Such a device providing increased accuracy in temperature measurement. The present invention also teaches a packaging substrate assembled with a semiconductor die having an opening in the substrate enabling the placement of a thermocouple such that it is in contact with the die and secured in place. Additionally, methods of constructing the devices of the present invention are disclosed.

    摘要翻译： 公开了一种用于在倒装芯片半导体封装期间获得精确热分布的热测量装置以及用于制造这种装置的方法。 特别地，包括夹在半导体封装基板和半导体管芯之间的热电偶的测量装置。 这种装置提供了更高的温度测量精度。 本发明还教导了组装有半导体管芯的封装衬底，该半导体管芯具有在衬底中的开口，使得能够放置热电偶，使得其与管芯接触并固定到位。 另外，公开了构成本发明的装置的方法。

    Dual chip in package with a wire bonded die mounted to a substrate
    7.
    发明授权
    Dual chip in package with a wire bonded die mounted to a substrate 有权
    双芯片封装，带有焊线芯片，安装在基板上

    公开(公告)号：US06586825B1

    公开(公告)日：2003-07-01

    申请号：US09843443

    申请日：2001-04-26

    申请人： Sarathy Rajagopalan ,  Kishor Desai ,  Maniam Alagaratnam

    发明人： Sarathy Rajagopalan ,  Kishor Desai ,  Maniam Alagaratnam

    IPC分类号： H05K116

    CPC分类号： H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/00012

    摘要： A package comprises a top die and a bottom die. The top die has top and bottom surfaces while the bottom die has top and bottom surfaces. The bottom die is mounted on a substrate, which has a top surface, such that the bottom surface of the bottom die faces the top surface of the substrate. The bottom surface of the top die is separated from the top surface of the bottom die by an interposer, which creates a space between the exterior regions of the top surface of the bottom die and the bottom surface of the top die. Each of a plurality of wires, which are electrically connected to the bottom die, runs through this space (i.e. runs between the top surface of the bottom die and the bottom surface of the top die), thereby permitting (if desired) the top die to be at least as large as the bottom die.

    摘要翻译： 包装包括顶模和底模。 顶部模具具有顶部和底部表面，而底部模具具有顶部和底部表面。 底模安装在具有顶表面的基底上，使得底模的底表面面向基底的顶表面。 顶部模具的底表面通过插入件与底模的顶表面分离，其在底模的顶表面的外部区域和顶模的底表面之间产生空间。 电连接到底模的多根导线中的每一根穿过该空间（即，在底模的顶表面和顶模的底表面之间延伸），从而允许（如果需要）顶模 至少与底部模具一样大。

    Method of protecting fuses in an integrated circuit die
    10.
    发明申请
    Method of protecting fuses in an integrated circuit die 审中-公开
    保护集成电路管芯中保险丝的方法

    公开(公告)号：US20060128072A1

    公开(公告)日：2006-06-15

    申请号：US11011459

    申请日：2004-12-13

    申请人： Sarathy Rajagopalan ,  Kishor Desai ,  Shirish Shah

    发明人： Sarathy Rajagopalan ,  Kishor Desai ,  Shirish Shah

    IPC分类号： H01L21/82

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A fuse formed in an integrated circuit die includes: a length of an electrically conductive material for connecting two points of a circuit on the integrated circuit die and for selectively breaking the connection by a pulse of electrical current sufficient to dissolve a portion of the electrically conductive material; a passivation layer formed over the length of electrically conductive material; and a protective coating formed over a portion of the length of electrically conductive material in addition to the passivation layer to avoid damage to the fuse from an etchant during a bumping process.

    摘要翻译： 形成在集成电路管芯中的保险丝包括：用于连接集成电路管芯上的电路的两个点的导电材料的长度，并且用于通过足以溶解导电的一部分的电流的脉冲来选择性地断开连接 材料; 形成在导电材料的长度上的钝化层; 以及除了钝化层之外还在导电材料长度的一部分上形成的保护涂层，以避免在碰撞过程中从蚀刻剂损坏保险丝。