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    Semiconductor memory device and refresh method thereof
    1.
    发明授权
    Semiconductor memory device and refresh method thereof 有权
    半导体存储器件及其刷新方法

    公开(公告)号：US09076504B2

    公开(公告)日：2015-07-07

    申请号：US13661773

    申请日：2012-10-26

    申请人： Jong-Ho Lee ,  Kyu-Chang Kang ,  Hyo-Chang Kim ,  Jae-Youn Youn ,  Sang-Jae Rhee

    发明人： Jong-Ho Lee ,  Kyu-Chang Kang ,  Hyo-Chang Kim ,  Jae-Youn Youn ,  Sang-Jae Rhee

    IPC分类号： G11C7/08 ,  G11C11/406 ,  G11C11/4091

    CPC分类号： G11C7/08 ,  G11C11/40626 ,  G11C11/4091 ,  G11C2211/4065 ,  G11C2211/4068

    摘要： A semiconductor memory device and a self-refresh method of the semiconductor memory device. The semiconductor memory device includes: a memory cell array including one or more memory cells; a sense amplifier connected to a sensing line and a complementary sensing line and sensing/amplifying data stored in the one or more memory cells; and a sense amplifier control circuit sequentially supplying a first voltage and a second voltage having different levels to the sense amplifier through the sensing line during a refresh operation.

    摘要翻译： 半导体存储器件和半导体存储器件的自刷新方法。 半导体存储器件包括：包括一个或多个存储单元的存储单元阵列; 连接到感测线和互补感测线的感测放大器，以及感测/放大存储在所述一个或多个存储器单元中的数据; 以及读出放大器控制电路，其在刷新操作期间通过感测线路顺序地将具有不同电平的第一电压和第二电压提供给读出放大器。

    Semiconductor memory device having split word line driver circuit with layout patterns that provide increased integration density
    3.
    发明授权
    Semiconductor memory device having split word line driver circuit with layout patterns that provide increased integration density 有权
    具有分离字线驱动电路的半导体存储器件具有提供增加的集成密度的布局图案

    公开(公告)号：US07729195B2

    公开(公告)日：2010-06-01

    申请号：US11935887

    申请日：2007-11-06

    申请人： Jae-Youn Youn ,  Yoon-Hwan Yoon ,  Sang-Jae Rhee

    发明人： Jae-Youn Youn ,  Yoon-Hwan Yoon ,  Sang-Jae Rhee

    IPC分类号： G11C8/00

    CPC分类号： G11C8/08 ,  G11C5/025 ,  G11C8/14

    摘要： Semiconductor memory devices having hierarchical word line structures are provided. A block of sub-word line driver circuits (SWDB) are disposed between a first block of memory and a second block of memory. A SWDB includes a plurality of sub-wordline driver (SWD) circuits arranged in a plurality of SWD columns each having four SWD circuits extending in a first direction between the first and second blocks of memory. Two adjacent SWD columns include a SWD group for driving a plurality of sub-word lines extending from the SWD group along the first direction into the first and second blocks of memory.

    摘要翻译： 提供具有分层字线结构的半导体存储器件。 一块子字线驱动电路（SWDB）设置在第一存储器块和第二存储器块之间。 SWDB包括布置在多个SWD列中的多个子字线驱动器（SWD）电路，每个SWD列具有在第一和第二存储器块之间沿第一方向延伸的四个SWD电路。 两个相邻的SWD列包括用于驱动从SWD组沿着第一方向延伸到第一和第二存储块的多个子字线的SWD组。

    SEMICONDUCTOR MEMORY DEVICE HAVING ANTIFUSE CIRCUITRY
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING ANTIFUSE CIRCUITRY 审中-公开
    具有抗病毒电路的半导体存储器件

    公开(公告)号：US20090059682A1

    公开(公告)日：2009-03-05

    申请号：US12202902

    申请日：2008-09-02

    申请人： Bok-Gue Park ,  Sang-Jae Rhee ,  Jae-Youn Youn

    发明人： Bok-Gue Park ,  Sang-Jae Rhee ,  Jae-Youn Youn

    IPC分类号： G11C7/00 ,  G11C29/00 ,  G11C8/00

    CPC分类号： G11C29/02 ,  G11C29/027 ,  G11C29/787

    摘要： A semiconductor memory device includes a fuse box including a plurality of address antifuse circuits, each address antifuse circuit outputting an address fuse signal according to a program state of an antifuse included in the corresponding address antifuse circuit, an address comparator including a plurality of address comparison signal generators, each address comparison signal generator combining a first test signal for determining an initial defect of the antifuse and a corresponding bit of an externally applied address signal to generate a test address, and comparing the test address with the address fuse signal to generate an address comparison signal, and a redundant enable signal generator for enabling a redundancy enable signal in response to a plurality of address comparison signals.

    摘要翻译： 一种半导体存储器件，包括一个包括多个地址反熔丝电路的保险丝盒，每个地址反熔丝电路根据相应的地址反熔丝电路中包括的反熔丝的编程状态输出地址熔丝信号，地址比较器包括多个地址比较 信号发生器，每个地址比较信号发生器组合用于确定反熔丝的初始缺陷的第一测试信号和外部施加的地址信号的相应位以产生测试地址，以及将测试地址与地址熔丝信号进行比较，以产生 地址比较信号，以及冗余使能信号发生器，用于响应于多个地址比较信号启用冗余使能信号。

    Internal voltage source generator in semiconductor memory device
    6.
    发明授权
    Internal voltage source generator in semiconductor memory device 有权
    半导体存储器件内部电压源发生器

    公开(公告)号：US06774712B2

    公开(公告)日：2004-08-10

    申请号：US10331602

    申请日：2002-12-31

    申请人： Sang-Jae Rhee ,  Jae-Yoon Sim ,  Sang-Pyo Hong ,  Ki-Chul Chun

    发明人： Sang-Jae Rhee ,  Jae-Yoon Sim ,  Sang-Pyo Hong ,  Ki-Chul Chun

    IPC分类号： G05F110

    CPC分类号： G05F1/465

    摘要： In this circuit, an external voltage source is supplied or down converted in response to a normal operating mode to provide the internal voltage source of a first level to the internal circuit. The external voltage source is converted to a voltage of a second level, lower than the first level, in response to a low consumption power mode having a complementary relation with the normal mode.

    摘要翻译： 在该电路中，响应于正常操作模式，提供或降低外部电压源，以向内部电路提供第一电平的内部电压源。 响应于与正常模式具有互补关系的低功耗模式，外部电压源被转换成低于第一电平的第二电平的电压。

    Semiconductor memory device having internal circuits responsive to temperature data and method thereof
    7.
    发明授权
    Semiconductor memory device having internal circuits responsive to temperature data and method thereof 失效
    具有响应于温度数据的内部电路的半导体存储器件及其方法

    公开(公告)号：US07554869B2

    公开(公告)日：2009-06-30

    申请号：US10981652

    申请日：2004-11-05

    申请人： Soo-Young Kim ,  Sang-Jae Rhee ,  Min-Gyu Hwang

    发明人： Soo-Young Kim ,  Sang-Jae Rhee ,  Min-Gyu Hwang

    IPC分类号： G11C7/04

    CPC分类号： G11C7/06 ,  G11C5/147 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  H03K3/012 ,  H03K17/164 ,  H03K2217/0036

    摘要： A semiconductor memory device having internal circuits responsive to temperature data, in order to compensate an output characteristic change of the internal circuits and reduce power consumption depending on temperature change, and method thereof are disclosed. The semiconductor memory device may include a temperature sensing circuit and an internal circuit. The temperature sensing circuit may generate and output temperature data in response to ambient temperature of the semiconductor memory device. The internal circuit may adjust an output level of an output signal in response to the temperature data from the temperature sensing circuit.

    摘要翻译： 具有响应于温度数据的内部电路的半导体存储器件及其方法被公开，以便补偿内部电路的输出特性变化并降低根据温度变化的功耗。 半导体存储器件可以包括温度检测电路和内部电路。 温度检测电路可以响应于半导体存储器件的环境温度产生和输出温度数据。 内部电路可以响应于来自温度感测电路的温度数据来调节输出信号的输出电平。

    Semiconductor memory device having an internal voltage generation circuit for selectively generating an internal voltage according to an external voltage level
    8.
    发明授权
    Semiconductor memory device having an internal voltage generation circuit for selectively generating an internal voltage according to an external voltage level 失效
    具有内部电压产生电路的半导体存储器件，用于根据外部电压电平选择性地产生内部电压

    公开(公告)号：US06930948B2

    公开(公告)日：2005-08-16

    申请号：US10621165

    申请日：2003-07-15

    申请人： Kyu-Chan Lee ,  Sang-Jae Rhee ,  Jung-Yong Choi ,  Jong-Hyun Choi ,  Jong-Sik Na ,  Jae-Hoon Kim

    发明人： Kyu-Chan Lee ,  Sang-Jae Rhee ,  Jung-Yong Choi ,  Jong-Hyun Choi ,  Jong-Sik Na ,  Jae-Hoon Kim

    IPC分类号： G11C5/14 ,  G11C11/00

    CPC分类号： G11C5/147

    摘要： An external high/low voltage compatible semiconductor memory device includes an internal voltage pad, an internal voltage generation circuit, and an internal voltage control signal generation circuit. The internal voltage pad connects a low external voltage with an internal voltage, and the internal voltage generation circuit generates an internal voltage in response to an internal voltage control signal and a high external voltage. The internal voltage control signal generation circuit generates an internal voltage control signal according to an high or low external voltage. Thus, a database of the semiconductor memory device can be managed without classifying the database into databases for the high voltage and databases for the low voltage because of the internal voltage control signal. In addition, the internal voltage level is stable because charges provided to the internal voltage are regulated according to a voltage level of the external voltage.

    摘要翻译： 外部高/低电压兼容半导体存储器件包括内部电压焊盘，内部电压产生电路和内部电压控制信号产生电路。 内部电压焊盘将低外部电压与内部电压连接，并且内部电压产生电路响应于内部电压控制信号和高外部电压而产生内部电压。 内部电压控制信号发生电路根据高或低的外部电压产生内部电压控制信号。 因此，由于内部电压控制信号，可以管理半导体存储器件的数据库，而不将数据库分类为用于低电压的高电压数据库和数据库。 此外，内部电压电平稳定，因为根据外部电压的电压电平调节提供给内部电压的电荷。

    Semiconductor memory devices and methods for sampling data therefrom based on a relative position of a memory cell array section containing the data
    9.
    发明授权
    Semiconductor memory devices and methods for sampling data therefrom based on a relative position of a memory cell array section containing the data 有权
    半导体存储器件和方法，用于根据包含数据的存储单元阵列部分的相对位置对其数据进行采样

    公开(公告)号：US06370068B2

    公开(公告)日：2002-04-09

    申请号：US09755977

    申请日：2001-01-05

    申请人： Sang-Jae Rhee

    发明人： Sang-Jae Rhee

    IPC分类号： G11C722

    CPC分类号： G11C7/1057 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051

    摘要： Semiconductor devices and methods of sampling data therefrom are provided in which data is sampled from a memory cell array based on a relative position of a memory cell array section that contains the data. A sense amplifier generates an output signal in response to an address of one or more cells in a memory cell array. A control circuit generates a sample control signal in response to at least a portion of the address (e.g., one or more high order bits of the address) of the one or more cells in the memory cell array. A data sampling circuit then samples the output signal of the sense amplifier in response to the sample control signal. The portion of the memory cell array address used to drive the control circuit may logically divide the memory cell array into two or more sections. The control circuit may adjust the timing of the sample control signal in accordance with the proximity of a memory cell array section to the sense amplifier.

    摘要翻译： 提供半导体器件及其数据采样方法，其中基于包含数据的存储单元阵列部分的相对位置从存储器单元阵列采样数据。 感测放大器响应于存储器单元阵列中的一个或多个单元的地址产生输出信号。 控制电路响应于存储器单元阵列中的一个或多个单元的地址的至少一部分（例如，地址的一个或多个高位）而产生采样控制信号。 然后，数据采样电路响应于采样控制信号对读出放大器的输出信号进行采样。 用于驱动控制电路的存储单元阵列地址的部分可逻辑地将存储单元阵列划分成两个或多个区段。 控制电路可以根据存储单元阵列部分与感测放大器的接近度来调整采样控制信号的定时。

    Internal source voltage generator for a semiconductor memory device
    10.
    发明授权
    Internal source voltage generator for a semiconductor memory device 失效
    用于半导体存储器件的内部源电压发生器

    公开(公告)号：US5946242A

    公开(公告)日：1999-08-31

    申请号：US883537

    申请日：1997-06-26

    申请人： Soo-In Cho ,  Sang-Jae Rhee

    发明人： Soo-In Cho ,  Sang-Jae Rhee

    IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/401 ,  G11C29/06 ,  G11C29/50 ,  G11C7/00

    CPC分类号： G11C5/147 ,  G11C29/50 ,  G11C11/401

    摘要： A circuit for generating an internal source voltage signal responsive to an external source voltage signal in a semiconductor memory device prevents malfunction and extends the lifetime of the device by clamping the internal source signal if the device is in a normal operating mode when the external source signal is in a stress operating range. When the device is placed in a test mode, the circuit allows the internal source signal to increase in proportion to the level of the external source signal when the external source signal is in a stress operating range. The circuit includes in internal source voltage generator, which always clamps the internal source signal when the external source signal is in a normal operating range, and a pull-up unit which is activated in response to a control signal. The control signal is enabled when the device is placed in a test mode by combining external timing signals.

    摘要翻译： 用于在半导体存储器件中产生响应于外部源极电压信号的内部源极电压信号的电路防止故障，并且如果器件处于正常工作模式时通过钳位内部源极信号来延长器件的寿命，当外部源极信号 处于压力操作范围。 当器件处于测试模式时，当外部源极信号处于应力工作范围时，该电路允许内部源极信号与外部源极信号的电平成正比。 该电路包括内部源电压发生器，当外部源极信号处于正常工作范围时，它始终夹紧内部源极信号，以及响应控制信号激活的上拉单元。 当通过组合外部定时信号将器件置于测试模式时，控制信号被使能。