公开(公告)号：US20210366538A1

公开(公告)日：2021-11-25

申请号：US17184980

申请日：2021-02-25

Applicant: KIOXIA CORPORATION

Inventor： Kosuke YANAGIDAIRA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  H01L25/065

Abstract: A semiconductor storage device includes a memory transistor and a word line connected to a gate electrode of the memory transistor. When a write sequence is interrupted before a k+1th verification operation is ended after a kth verification operation is ended in the nth write loop of the write sequence, a voltage equal to or higher than a verification voltage corresponding to a first verification operation in the nth write loop is supplied to the word line before start of the k+1th verification operation after resumption of the write sequence. A time from the resumption of the write sequence to the start of the k+1th verification operation is shorter than a time from start of the first verification operation to end of the kth verification operation in the nth write loop.

公开(公告)号：US20230290406A1

公开(公告)日：2023-09-14

申请号：US18318417

申请日：2023-05-16

Applicant: Kioxia Corporation

Inventor： Kosuke YANAGIDAIRA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  H01L25/065 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  H01L25/0657 ,  G11C16/3459 ,  H01L2225/06506 ,  H01L2225/06562 ,  H10B41/27

Abstract: A semiconductor storage device includes a memory transistor and a word line connected to a gate electrode of the memory transistor. When a write sequence is interrupted before a k+1th verification operation is ended after a kth verification operation is ended in the nth write loop of the write sequence, a voltage equal to or higher than a verification voltage corresponding to a first verification operation in the nth write loop is supplied to the word line before start of the k+1th verification operation after resumption of the write sequence. A time from the resumption of the write sequence to the start of the k+1th verification operation is shorter than a time from start of the first verification operation to end of the kth verification operation in the nth write loop.

公开(公告)号：US20250046382A1

公开(公告)日：2025-02-06

申请号：US18926712

申请日：2024-10-25

Applicant: KIOXIA CORPORATION

Inventor： Kosuke YANAGIDAIRA

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/32 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a semiconductor memory device includes a first conductor extending in a first direction, bit lines, sense amplifiers, and a second conductor extending in the first direction. A plurality of first memory cells being connected to the first conductor. The bit lines respectively connected to the first memory cells. The first sense amplifiers are respectively connected to a plurality of first bit lines included in the bit lines, each of the first sense amplifiers including a first sense node, and a first transistor connected between the first sense node and a corresponding one of the first bit lines. The second conductor function as gate electrodes of the first transistors included in the first sense amplifiers.

公开(公告)号：US20230410916A1

公开(公告)日：2023-12-21

申请号：US18362289

申请日：2023-07-31

Applicant: KIOXIA CORPORATION

Inventor： Kosuke YANAGIDAIRA

IPC: G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  G11C16/08 ,  G11C16/32 ,  G11C16/24 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/32 ,  G11C16/10 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  G11C16/24

Abstract: According to one embodiment, a semiconductor memory device includes a first conductor extending in a first direction, bit lines, sense amplifiers, and a second conductor extending in the first direction. A plurality of first memory cells being connected to the first conductor. The bit lines respectively connected to the first memory cells. The first sense amplifiers are respectively connected to a plurality of first bit lines included in the bit lines, each of the first sense amplifiers including a first sense node, and a first transistor connected between the first sense node and a corresponding one of the first bit lines. The second conductor function as gate electrodes of the first transistors included in the first sense amplifiers.

公开(公告)号：US20220344256A1

公开(公告)日：2022-10-27

申请号：US17860345

申请日：2022-07-08

Applicant: KIOXIA CORPORATION

Inventor： Kosuke YANAGIDAIRA ,  Chikaaki KODAMA

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/02 ,  H01L23/48

Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

公开(公告)号：US20220337457A1

公开(公告)日：2022-10-20

申请号：US17857022

申请日：2022-07-03

Applicant: KIOXIA CORPORATION

Inventor： Kensuke YAMAMOTO ,  Kosuke YANAGIDAIRA

IPC: H04L25/02 ,  G11C29/02 ,  G11C11/4093 ,  G11C7/10 ,  G11C11/16 ,  G11C11/409 ,  H03K19/00 ,  H03K19/17764

Abstract: A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.

公开(公告)号：US20220139467A1

公开(公告)日：2022-05-05

申请号：US17575554

申请日：2022-01-13

Applicant: KIOXIA CORPORATION

Inventor： Kosuke YANAGIDAIRA ,  Mario SAKO

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56 ,  G11C16/30 ,  G11C16/24

Abstract: A semiconductor memory includes memory cells, a word line and bit lines of the memory cells, sense amplifiers connected to the bit lines, respectively, and a controller. Each sense amplifier includes first, second, and third transistors. The third transistor has one end connected to each of the first and second transistors, and the other end connected to a corresponding bit line. During a read operation, at a first time of a first period during which the controller applies a first read voltage to the word line, the controller applies a first voltage higher than ground voltage to the first transistor, and a second voltage to the second transistor. Also, at the first time, a first sense amplifier applies a voltage to a first bit line through its first and third transistors, and a second sense amplifier applies a voltage to a second bit line through the second and third transistors.

公开(公告)号：US20220093174A1

公开(公告)日：2022-03-24

申请号：US17184246

申请日：2021-02-24

Applicant: KIOXIA CORPORATION

Inventor： Yuki SHIMIZU ,  Kosuke YANAGIDAIRA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/26

Abstract: A semiconductor storage device includes a first plane storing user data and system information, a second plane storing the user data and the system information, a first latch circuit storing even-numbered bit data of the system information read from the first plane, a second latch circuit storing odd-numbered bit data of the system information read from the second plane, and a sequencer. The sequencer executes in parallel a first process of reading out the even-numbered bit data of the system information from the first plane and storing the read data in the first latch circuit and a second process of reading out the odd-numbered bit data of the system information from the second plane and storing the read data in the second latch circuit.

公开(公告)号：US20210327515A1

公开(公告)日：2021-10-21

申请号：US17363005

申请日：2021-06-30

Applicant: KIOXIA CORPORATION

Inventor： Kosuke YANAGIDAIRA ,  Hiroshi TSUBOUCHI

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/32 ,  H01L27/11582 ,  H01L27/11565 ,  G11C16/08

Abstract: A semiconductor memory device includes a controller which executes a read operation. In the read operation, the controller applies first and second read voltages to a word line, reads data at each of first and second times, applies the first voltage to a source line at each of the first and second times, applies a second voltage to the source line during the application of the first read voltage to the word line and before the first time, and applies a third voltage to the source line during the application of the second read voltage to the word line and before the second time.

公开(公告)号：US20250069670A1

公开(公告)日：2025-02-27

申请号：US18946968

申请日：2024-11-14

Applicant: Kioxia Corporation

Inventor： Kosuke YANAGIDAIRA ,  Hiroshi TSUBOUCHI

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/32 ,  H10B43/10 ,  H10B43/27

Abstract: A memory system includes a semiconductor memory device and a memory controller configured to send a command to the device. The device includes a memory cell connected between a bit line and a source line, a sense amplifier having a first transistor provided between at least two transistors of the sense amplifier and the bit line, and a sequencer. The sequencer, in response to the command, reads data stored by the memory cell by applying a first voltage to the first transistor and a second voltage to the source line during a first time period, applying a third voltage to the first transistor and a fourth voltage to the source line during a second time period after the first time period, and applying the first voltage to the first transistor and a fifth voltage to the source line during a third time period after the second time period.