公开(公告)号：US11765916B2

公开(公告)日：2023-09-19

申请号：US17348839

申请日：2021-06-16

Applicant: Kioxia Corporation

Inventor： Takahiko Iizuka ,  Daisaburo Takashima ,  Ryu Ogiwara ,  Rieko Funatsuki ,  Yoshiki Kamata ,  Misako Morota ,  Yoshiaki Asao ,  Yukihiro Nomura

IPC: G11C11/00 ,  H10B63/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/845 ,  G11C13/003 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  H10B63/34 ,  H10N70/066 ,  H10N70/231 ,  H10N70/8828 ,  G11C2213/75

Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.

公开(公告)号：US11715527B2

公开(公告)日：2023-08-01

申请号：US17458059

申请日：2021-08-26

Applicant: KIOXIA CORPORATION

Inventor： Kazutaka Ikegami ,  Hidehiro Shiga ,  Takashi Maeda ,  Rieko Funatsuki ,  Takayuki Miyazaki

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C16/20 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/20 ,  G11C16/30 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor storage device includes a semiconductor pillar, a first string having first memory cells connected in series, first word lines connected to the first memory cells, a second string having second memory cells connected in series, and second word lines connected to the second memory cells. Each of the first memory cells faces, and shares a channel in the semiconductor pillar with, one of the second memory cells. When reading data of the k-th first memory cell, a voltage of the first word line connected to the k-th first memory cell reaches a first voltage at a first timing, and a voltage of the second word line connected to at least one of the second memory cells other than the k-th second memory cell in the second string facing the k-th first memory cell reaches the first voltage at a second timing that is later than the first timing.

公开(公告)号：US11715534B2

公开(公告)日：2023-08-01

申请号：US17459441

申请日：2021-08-27

Applicant: KIOXIA CORPORATION

Inventor： Rieko Funatsuki ,  Takashi Maeda ,  Reiko Sumi ,  Reika Tanaka ,  Masumi Saitoh

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/04

CPC classification number: G11C16/3445 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3404

Abstract: A semiconductor storage device includes a memory cell array including a plurality of memory strings, each connected between one of a plurality of bit lines and a source line and includes a first select transistor, a second select transistor, and memory cell transistors that are connected in series between the first select transistor and the second select transistor, and a plurality of word lines respectively connected to gates of the memory cell transistors in each memory string. A threshold voltage of the memory cell transistor is increased when a voltage that is applied to the word line connected to the gate thereof is lower than a voltage of a channel thereof. In the erase operation, data stored in the memory cell transistors connected to a selected one of the word lines are erased while data stored in the memory cell transistors not connected to the selected word line are not erased.

公开(公告)号：US11769554B2

公开(公告)日：2023-09-26

申请号：US17447464

申请日：2021-09-13

Applicant: Kioxia Corporation

Inventor： Kyosuke Sano ,  Kazutaka Ikegami ,  Takashi Maeda ,  Rieko Funatsuki

IPC: G11C11/34 ,  G11C16/26 ,  G11C16/30 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/30 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor memory device of embodiments includes: a substrate; a memory pillar; first to sixth conductive layers provided above the substrate; first to sixth memory cells formed between the first to sixth conductive layers and the memory pillar, respectively; and a control circuit. The control circuit applies a first voltage to the first, second, a sixth conductive layer and applies a second voltage to the third, fifth conductive layer, then applies a third voltage to the first conductive layer, applies a fourth voltage to the sixth conductive layer, and applies a fifth voltage to the second conductive layer, and then applies a sixth voltage to the first conductive layer, applies a seventh voltage to the sixth conductive layer, and applies an eighth voltage lower than the fifth voltage to the second conductive layer.

公开(公告)号：US11282578B2

公开(公告)日：2022-03-22

申请号：US16906140

申请日：2020-06-19

Applicant: Kioxia Corporation

Inventor： Rieko Funatsuki ,  Takahiko Hara ,  Takashi Maeda

IPC: G11C16/26 ,  G11C16/04 ,  H01L27/115

Abstract: A semiconductor storage apparatus includes a memory cell array including a plurality of memory string structures each including a pair of memory string formation sections each formed by a channel formation film and a charge storage film and including a select gate transistor and a plurality of memory cell transistors connected in series and a partial conductive layer configured to electrically connect the memory string formation sections. During a reading operation of a memory cell transistor, at least one of the plurality of memory cell transistors and the select gate transistor belonging to the memory string formation section is turned off such that a channel of a memory cell transistor is fixed to a potential of a source line or a potential of bit lines.

公开(公告)号：US11282559B1

公开(公告)日：2022-03-22

申请号：US17201114

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Reika Tanaka ,  Masumi Saitoh ,  Takashi Maeda ,  Rieko Funatsuki ,  Hidehiro Shiga

IPC: G11C11/22 ,  H01L27/11597

Abstract: According to one embodiment, a memory device includes: a third layer between first and a second layers above a substrate; a pillar being adjacent to the first to third layers and including a ferroelectric layer; a memory cell between the third layer and the pillar; and a circuit which executes a first operation for a programming, a second operation for an erasing using a first voltage, and a third operation of applying a second voltage between the third layer and the pillar. The first voltage has a first potential difference, the second voltage has a second potential difference smaller than the first potential difference. A potential of the third conductive layer is lower than a potential of the pillar in each of the first and second voltages. The third operation is executed between the first operation and the second operation.

公开(公告)号：US11049573B2

公开(公告)日：2021-06-29

申请号：US16802471

申请日：2020-02-26

Applicant: KIOXIA CORPORATION

Inventor： Rieko Funatsuki ,  Takashi Maeda ,  Hidehiro Shiga ,  Hiroshi Maejima

IPC: G11C16/28 ,  G11C16/24 ,  G11C16/08 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11529 ,  H01L27/11573

Abstract: A semiconductor storage device includes a first memory cell and a second memory cell which are connected to each other in series, a first word line which is connected to the first memory cell, a second word line which is connected to the second memory cell, and a control circuit. The control circuit is configured to charge a first node while applying a second voltage to the second word line and a first voltage to the first word line, to charge a second node on the basis of a voltage of the charged first node, to discharge the second node while applying the second voltage to the second word line and a third voltage to the first word line, and to read data from the first memory cell on the basis of voltages of the charged and discharged second node.

公开(公告)号：US12211551B2

公开(公告)日：2025-01-28

申请号：US18177704

申请日：2023-03-02

Applicant: Kioxia Corporation

Inventor： Natsuki Sakaguchi ,  Takashi Maeda ,  Rieko Funatsuki ,  Hidehiro Shiga

IPC: G11C16/04 ,  G11C7/06 ,  G11C16/24

Abstract: A control circuit of a semiconductor memory device performs a write operation on a memory cell transistor of the semiconductor memory device by performing a first pulse application operation of lowering a threshold voltage of the memory cell transistor, a precharge operation, and then a second pulse application operation. In the precharge operation, in a state in which first and second select transistors connected to the memory cell transistor are turned on, a bit line connected to the memory cell transistor is charged by applying a ground voltage to a word line connected to a gate of the memory cell transistor and applying a voltage higher than the ground voltage to a source line. In the second pulse application operation, in a state in which the first select transistor is turned on and the second select transistor is turned off, a program voltage is applied to the word line.

公开(公告)号：US12159040B2

公开(公告)日：2024-12-03

申请号：US17899974

申请日：2022-08-31

Applicant: KIOXIA CORPORATION

Inventor： Rieko Funatsuki ,  Takashi Maeda ,  Sumiko Domae ,  Kazutaka Ikegami

IPC: G06F3/06

Abstract: A semiconductor memory device includes a semiconductor pillar including first and second memory cells electrically connected in series and formed on opposite sides of the semiconductor pillar, first word lines connected to the first memory cells, respectively, and second word lines connected to the second memory cells, respectively. A verify operation includes a channel clean operation for supplying a reference voltage to a semiconductor channel shared by the first and second memory cells followed by at least first and second sense operation for determining whether a threshold voltage of a target memory cell has reached first and second threshold voltage states, respectively, then a second channel clean operation for supplying the reference voltage to the semiconductor channel, and then at least a third sense operation for determining whether the threshold voltage of the target memory cell has reached a third threshold voltage state.

公开(公告)号：US12069872B2

公开(公告)日：2024-08-20

申请号：US18231304

申请日：2023-08-08

Applicant: Kioxia Corporation

Inventor： Takahiko Iizuka ,  Daisaburo Takashima ,  Ryu Ogiwara ,  Rieko Funatsuki ,  Yoshiki Kamata ,  Misako Morota ,  Yoshiaki Asao ,  Yukihiro Nomura

IPC: G11C11/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/845 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  H10B63/34 ,  H10N70/066 ,  H10N70/231 ,  H10N70/8828 ,  G11C2213/75

Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.