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    Controller for controlling non-volatile semiconductor memory and method of controlling non-volatile semiconductor memory
    3.
    发明授权
    Controller for controlling non-volatile semiconductor memory and method of controlling non-volatile semiconductor memory 有权

    公开(公告)号：US12259813B2

    公开(公告)日：2025-03-25

    申请号：US18624930

    申请日：2024-04-02

    Applicant: KIOXIA CORPORATION

    Inventor： Kazuhiro Fukutomi ,  Kenichiro Yoshii ,  Shinichi Kanno ,  Shigehiro Asano

    IPC: G06F12/02 ,  G06F3/06 ,  G06F12/00 ,  G06F12/16 ,  G06F13/16

    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.

    Media error reporting improvements for storage drives
    5.
    发明授权
    Media error reporting improvements for storage drives 有权

    公开(公告)号：US11482294B2

    公开(公告)日：2022-10-25

    申请号：US17335546

    申请日：2021-06-01

    Applicant: Kioxia Corporation

    Inventor： Neil Buxton ,  Shigehiro Asano ,  Steven Wells ,  Mark Carlson

    IPC: G06F11/08 ,  G06F13/00 ,  G11C11/34 ,  G11C16/04 ,  G11C29/00 ,  G11C29/04 ,  G06F11/07 ,  G06F11/30 ,  G06F11/10 ,  G06F3/06

    Abstract: A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.

    Memory system and method
    6.
    发明授权
    Memory system and method 有权

    公开(公告)号：US11372753B2

    公开(公告)日：2022-06-28

    申请号：US16433148

    申请日：2019-06-06

    Applicant: KIOXIA CORPORATION

    Inventor： Shigehiro Asano

    IPC: G06F12/00 ,  G06F13/00 ,  G06F12/02 ,  G11C11/56 ,  G11C16/16 ,  G11C16/08 ,  G11C16/30 ,  G06F3/06 ,  G06F12/1045 ,  G06F12/1009

    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller selects, as a write mode, at least one of a first mode in which N-bit data is written per memory cell in the nonvolatile memory and a second mode in which M-bit data is written per memory cell in the nonvolatile memory as a write mode. N is equal to or larger than one. M is larger than N. The controller selects the second mode when a reception speed of data, which is received in accordance with acceptance of one or more write commands from the host, is equal to or slower than a threshold, and selects the first mode when the reception speed is faster than the threshold.

    Memory system and memory control method
    9.
    发明授权
    Memory system and memory control method 有权

    公开(公告)号：US11727998B2

    公开(公告)日：2023-08-15

    申请号：US17512394

    申请日：2021-10-27

    Applicant: KIOXIA CORPORATION

    Inventor： Shigehiro Asano ,  Neil Buxton ,  Julien Margetts ,  Shunichi Igahara ,  Takehiko Amaki

    IPC: G11C16/26 ,  G11C16/34 ,  G11C8/12 ,  G11C16/04

    CPC classification number: G11C16/3431 ,  G11C8/12 ,  G11C16/26 ,  G11C16/3495 ,  G11C16/0483

    Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.

    Device and method for high performance memory debug record generation and management
    10.
    发明授权
    Device and method for high performance memory debug record generation and management 有权

    公开(公告)号：US11847037B2

    公开(公告)日：2023-12-19

    申请号：US17022943

    申请日：2020-09-16

    Applicant: KIOXIA CORPORATION

    Inventor： Paul Edward Hanham ,  Shigehiro Asano ,  Julien Margetts

    IPC: G06F11/00 ,  G06F11/30 ,  G06F11/32 ,  G06F3/06 ,  G06F11/36

    CPC classification number: G06F11/3075 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0683 ,  G06F11/3037 ,  G06F11/328 ,  G06F11/3656

    Abstract: Example implementations include a method of receiving a host command identifier associated with a host command, determining a device command associated with the host command and a memory controller device, receiving a device command timestamp corresponding to a time of the determining the device command, and determining a debug record contemporaneously with the determining the device command, the debug record including the host command identifier, a device command identifier associated with the device command, and the device command timestamp. Example implementations also include a device operably coupled to a memory array, and with a memory controller device configured to receive a host command identifier associated with a host command, and configured to determine a device command associated with the host command and a memory controller device, and a debug record generator device operatively coupled to the memory controller device and configured to receive a device command timestamp corresponding to a time of the determined device command, and configured to determine a debug record contemporaneously with the determining the device command, the debug record including the host command identifier, a device command identifier associated with the device command, and the device command timestamp.

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