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公开(公告)号：US07969751B2
公开(公告)日：2011-06-28
申请号：US12216737
申请日：2008-07-10
IPC分类号： H02B1/26
CPC分类号： H05K7/1458 , G06F1/185
摘要： A high-speed signal transmission apparatus comprises: a housing; a plurality of daughter boards juxtaposed to one another in the housing; board-side connectors each provided on corresponding each of the juxtaposed daughter boards; and cable-side connectors fixed in the housing; wherein each of the board-side connectors is insertable/removable into/from corresponding each of the cable-side connectors, and wherein a cable group whose impedance matching can be achieved makes connection between the predetermined cable-side connectors.
摘要翻译： 高速信号传输装置包括：壳体; 多个子板在壳体中彼此并置; 每个并置的子板上设置的板侧连接器; 和固定在壳体中的电缆侧连接器; 其中每个电路板侧连接器可插入/移除相应的每个电缆侧连接器，并且其中可实现阻抗匹配的电缆组在预定电缆侧连接器之间进行连接。
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公开(公告)号：US20090027867A1
公开(公告)日：2009-01-29
申请号：US12216737
申请日：2008-07-10
IPC分类号： H01R12/14
CPC分类号： H05K7/1458 , G06F1/185
摘要： A high-speed signal transmission apparatus comprises: a housing; a plurality of daughter boards juxtaposed to one another in the housing; board-side connectors each provided on corresponding each of the juxtaposed daughter boards; and cable-side connectors fixed in the housing; wherein each of the board-side connectors is insertable/removable into/from corresponding each of the cable-side connectors, and wherein a cable group whose impedance matching can be achieved makes connection between the predetermined cable-side connectors.
摘要翻译： 高速信号传输装置包括：壳体; 多个子板在壳体中彼此并置; 每个并置的子板上设置的板侧连接器; 和固定在壳体中的电缆侧连接器; 其中每个电路板侧连接器可插入/移除相应的每个电缆侧连接器，并且其中可实现阻抗匹配的电缆组在预定电缆侧连接器之间进行连接。
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3.发明申请OUTPUT BUFFER CIRCUIT, DIFFERENTIAL OUTPUT BUFFER CIRCUIT, OUTPUT BUFFER CIRCUIT HAVING REGULATION CIRCUIT AND REGULATION FUNCTION, AND TRANSMISSION METHOD 有权输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路及传输方式公开(公告)号：US20090179666A1
公开(公告)日：2009-07-16
申请号：US12343521
申请日：2008-12-24
申请人： Norio Chujo , Keiichi Yamamoto , Hisaaki Kanai , Toru Yazaki
发明人： Norio Chujo , Keiichi Yamamoto , Hisaaki Kanai , Toru Yazaki
IPC分类号： H03K19/003 , H03K19/0175
CPC分类号： H04L25/0278 , H04L25/028
摘要： An output buffer circuit, a differential output buffer circuit, an output buffer circuit having a regulation circuit and a regulation function, and a transmission method, capable of improving resolution of a pre-emphasis amount without increasing power consumption or a circuit area, in which the output buffer circuit 10 has a function which includes a delay circuit 23, an inverter 22 and output buffers 3 to 7 to transmit a logical signal to a transmission line 2 and generate a waveform having four or more types of signal voltages on a transmission side according to a signal attenuation amount of the transmission line 2 and the output buffer 3 has a variable resistance portion 12 at an on-resistance to change a pre-emphasis amount according to a change in a variable resistance value. The output buffer 3 has a selector 20 on a forward stage and a variable resistance portion 12 at an on-resistance. The inverter 22 is configured to select a signal to be input into the output buffer 6 according to a selector logic, invert a data signal and adjust a tap pre-emphasis amount by a select signal of the selector logic.
摘要翻译： 输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路以及传输方法，能够提高预加重量的分辨率而不增加功耗或电路面积，其中 输出缓冲电路10具有包括延迟电路23，反相器22和输出缓冲器3〜7的功能，以将逻辑信号发送到传输线2，并在发送侧产生具有四种或更多种信号电压的波形 根据传输线2的信号衰减量，输出缓冲器3具有导通电阻的可变电阻部分12，以根据可变电阻值的变化改变预加重量。 输出缓冲器3具有前级上的选择器20和导通电阻的可变电阻部分12。 反相器22被配置为根据选择器逻辑选择要输入到输出缓冲器6的信号，反转数据信号，并通过选择器逻辑的选择信号来调整抽头预加重量。
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4.发明申请Semiconductor Circuit, and Computing Device and Communications Device Using the Same 有权半导体电路和使用其的计算设备和通信设备公开(公告)号：US20090085688A1
公开(公告)日：2009-04-02
申请号：US12145829
申请日：2008-06-25
申请人： Keiichi YAMAMOTO , Norio Chujo , Toru Yazaki , Hisaaki Kanai
发明人： Keiichi YAMAMOTO , Norio Chujo , Toru Yazaki , Hisaaki Kanai
IPC分类号： H03H11/30
CPC分类号： H03F3/3028 , H01L2924/19051 , H03F1/308 , H03F2200/447 , H03F2200/453 , H03K19/017581
摘要： In a semiconductor circuit, an impedance adjustment circuit having the characteristics same as those of a circuit having the nonlinear resistance characteristics is configured to include an operating point calculation circuit automatically calculating an operating point with a reference resistance through feedback control, and an impedance calculation circuit calculating the impedance at the operating point found by the operating point calculation circuit. The impedance adjustment circuit is also provided with an impedance determination circuit that determines whether or not the impedance found by the impedance calculation circuit is in a predetermined range. These components, i.e., the operating point calculation circuit, the impedance calculation circuit, and the impedance determination circuit, are provided each two for High-side and Low-side impedance adjustment use.
摘要翻译： 在半导体电路中，具有与具有非线性电阻特性的电路相同特性的阻抗调整电路被配置为包括工作点计算电路，通过反馈控制自动计算具有参考电阻的工作点，以及阻抗计算电路 计算由工作点计算电路找到的工作点处的阻抗。 阻抗调整电路还设置有阻抗确定电路，其确定由阻抗计算电路发现的阻抗是否在预定范围内。 这两个部件，即工作点计算电路，阻抗计算电路和阻抗确定电路，每两个用于高侧和低侧阻抗调节。
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5.发明申请SIGNAL DELAY CIRCUIT AND DRIVER CIRCUIT, SIGNAL TRANSMISSION MODULE, AND SIGNAL TRANSMISSION SYSTEM USING SIGNAL DELAY CIRCUIT 审中-公开使用信号延迟电路的信号延迟电路和驱动电路，信号传输模块和信号传输系统公开(公告)号：US20080036512A1
公开(公告)日：2008-02-14
申请号：US11834714
申请日：2007-08-07
申请人： Keiichi Yamamoto , Norio Chujo
发明人： Keiichi Yamamoto , Norio Chujo
CPC分类号： H03H11/265 , H03K5/133 , H03K2005/0013
摘要： A signal delay circuit includes: a first inverter circuit; a second inverter circuit connected to an output terminal of the first inverter; and a feedback circuit extending from an output terminal of the second inverter to its input terminal. A delay time of the first inverter circuit is adjusted by controlling the amount of feedback through the feedback circuit. Here, the feedback circuit is formed by MOS transistors and the delay time is adjusted by controlling the gate voltages of the MOS transistors. The feedback amount is adjusted in relation to a variation in a power supply voltage and a variation in the delay time of the signal delay circuit is suppressed.
摘要翻译： 信号延迟电路包括：第一反相器电路; 连接到第一反相器的输出端的第二反相器电路; 以及从第二反相器的输出端子延伸到其输入端子的反馈电路。 通过控制通过反馈电路的反馈量来调节第一反相器电路的延迟时间。 这里，反馈电路由MOS晶体管形成，并且通过控制MOS晶体管的栅极电压来调整延迟时间。 相对于电源电压的变化来调整反馈量，抑制了信号延迟电路的延迟时间的变化。
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公开(公告)号：US06979810B2
公开(公告)日：2005-12-27
申请号：US09930806
申请日：2001-08-15
申请人： Norio Chujo , Keiichi Yamamoto , Akio Osaki , Katsunori Hirano , Takayuki Nakao , Tomoaki Shimotsu , Atsushi Hasegawa , Tetsuya Aoki , Takeshi Yamashita
发明人： Norio Chujo , Keiichi Yamamoto , Akio Osaki , Katsunori Hirano , Takayuki Nakao , Tomoaki Shimotsu , Atsushi Hasegawa , Tetsuya Aoki , Takeshi Yamashita
IPC分类号： H01L31/10 , H01L31/107 , H03L7/085 , H03L7/091 , H04B10/07 , H04B10/2507 , H04B10/40 , H04B10/50 , H04B10/60 , H04L7/033 , H01J40/14 , H03D3/24 , H04B10/06
摘要： A sample & hold type phase detector is used in a CDR IC and, in jitter transfer bandwidth adjustment, VCO output waveforms 90° out of phase with each other can be inputted to the phase detector, whereby a jitter transfer bandwidth can be calculated by only the measurement of frequency and of a DC voltage and it is possible to make a jitter transfer bandwidth adjustment in DC test for IC.
摘要翻译： 在CDR IC中使用采样保持型相位检测器，并且在抖动传输带宽调整中，彼此相位差90°的VCO输出波形可以被输入到相位检测器，由此抖动传输带宽可以仅通过 频率和直流电压的测量，可以在IC的直流测试中进行抖动传输带宽调整。
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7.发明授权Semiconductor circuit, and computing device and communications device using the same 有权半导体电路，以及使用它的计算设备和通信设备公开(公告)号：US07902860B2
公开(公告)日：2011-03-08
申请号：US12145829
申请日：2008-06-25
申请人： Keiichi Yamamoto , Norio Chujo , Toru Yazaki , Hisaaki Kanai
发明人： Keiichi Yamamoto , Norio Chujo , Toru Yazaki , Hisaaki Kanai
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03F3/3028 , H01L2924/19051 , H03F1/308 , H03F2200/447 , H03F2200/453 , H03K19/017581
摘要： In a semiconductor circuit, an impedance adjustment circuit having the characteristics same as those of a circuit having the nonlinear resistance characteristics is configured to include an operating point calculation circuit automatically calculating an operating point with a reference resistance through feedback control, and an impedance calculation circuit calculating the impedance at the operating point found by the operating point calculation circuit. The impedance adjustment circuit is also provided with an impedance determination circuit that determines whether or not the impedance found by the impedance calculation circuit is in a predetermined range. These components, i.e., the operating point calculation circuit, the impedance calculation circuit, and the impedance determination circuit, are provided each two for High-side and Low-side impedance adjustment use.
摘要翻译： 在半导体电路中，具有与具有非线性电阻特性的电路相同特性的阻抗调整电路被配置为包括工作点计算电路，通过反馈控制自动计算具有参考电阻的工作点，以及阻抗计算电路 计算由工作点计算电路找到的工作点处的阻抗。 阻抗调整电路还设置有阻抗确定电路，其确定由阻抗计算电路发现的阻抗是否在预定范围内。 这两个部件，即工作点计算电路，阻抗计算电路和阻抗确定电路，每两个用于高侧和低侧阻抗调节。
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8.发明授权Output buffer circuit, differential output buffer circuit, output buffer circuit having regulation circuit and regulation function, and transmission method 有权输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路及传输方式公开(公告)号：US07772877B2
公开(公告)日：2010-08-10
申请号：US12343521
申请日：2008-12-24
申请人： Norio Chujo , Keiichi Yamamoto , Hisaaki Kanai , Toru Yazaki
发明人： Norio Chujo , Keiichi Yamamoto , Hisaaki Kanai , Toru Yazaki
IPC分类号： H03K19/003
CPC分类号： H04L25/0278 , H04L25/028
摘要： An output buffer circuit, a differential output buffer circuit, an output buffer circuit having a regulation circuit and a regulation function, and a transmission method, to improve resolution of a pre-emphasis amount without increasing power consumption or a circuit area. The output buffer includes a delay circuit, an inverter and output buffers to transmit a logical signal to a transmission line and generate a waveform having four or more types of signal voltages on a transmission side according to a signal attenuation amount of the transmission line. The output buffer has a selector and a variable resistance portion at an output resistance to change a pre-emphasis amount according to a change in a variable resistance value. The inverter is configured to select a signal to input into the output buffer, invert a data signal and adjust a tap pre-emphasis amount by a select signal of the selector logic.
摘要翻译： 输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路以及传输方法，以提高预加重量的分辨率，而不增加功耗或电路面积。 输出缓冲器包括延迟电路，反相器和输出缓冲器，以将逻辑信号传输到传输线，并根据传输线的信号衰减量产生在发送侧具有四种或更多种类型的信号电压的波形。 输出缓冲器具有输出电阻的选择器和可变电阻部分，以根据可变电阻值的变化改变预加重量。 逆变器被配置为选择要输入到输出缓冲器的信号，反转数据信号并通过选择器逻辑的选择信号调整抽头预加重量。
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公开(公告)号：US09698783B2
公开(公告)日：2017-07-04
申请号：US14122623
申请日：2012-05-24
申请人： Wen Li , Norio Chujo , Masami Makuuchi , Takehito Kamimura
发明人： Wen Li , Norio Chujo , Masami Makuuchi , Takehito Kamimura
IPC分类号： H03K19/0175 , H03F1/52 , H03F3/195 , H03F3/21 , H03F3/30
CPC分类号： H03K19/0175 , H01L2224/48137 , H01L2924/181 , H03F1/52 , H03F3/195 , H03F3/211 , H03F3/3022 , H03F2200/189 , H03K19/017509 , H01L2924/00012
摘要： Provided is a configuration of a driver integrated circuit that can output a voltage exceeding the withstand voltage of a process, and that satisfies required apparatus performance (high speed and high voltage). A differential input circuit, a level shift circuit, and an output circuit are manufactured by the same process and divided and disposed on three or more chips with different substrate potentials (sub-potentials). By setting different applied voltages to the substrates of the chips, an output voltage greater than the process withstand voltage can be provided (see FIG. 2).
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公开(公告)号：US08451063B2
公开(公告)日：2013-05-28
申请号：US12892988
申请日：2010-09-29
IPC分类号： H03F3/08
CPC分类号： H03F1/08 , H03F3/45098 , H03F2200/213 , H03F2200/261 , H03F2200/411 , H03F2203/45458
摘要： A circuit having a sensor with a stray capacitance value. An output from the sensor is connected to the input of an amplifier while a negative capacitance circuit is electrically connected in parallel with the sensor output. The negative capacitance circuit reduces the effect of the sensor stray capacitance to provide an increased bandwidth and decreased noise on the amplifier output.
摘要翻译： 具有具有杂散电容值的传感器的电路。 传感器的输出连接到放大器的输入端，而负电容电路与传感器输出端并联电连接。 负电容电路降低了传感器杂散电容的影响，从而提高了放大器输出端的带宽和降低的噪声。
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