公开(公告)号：US20090179666A1

公开(公告)日：2009-07-16

申请号：US12343521

申请日：2008-12-24

申请人： Norio Chujo ,  Keiichi Yamamoto ,  Hisaaki Kanai ,  Toru Yazaki

发明人： Norio Chujo ,  Keiichi Yamamoto ,  Hisaaki Kanai ,  Toru Yazaki

IPC分类号： H03K19/003 ,  H03K19/0175

CPC分类号： H04L25/0278 ,  H04L25/028

摘要： An output buffer circuit, a differential output buffer circuit, an output buffer circuit having a regulation circuit and a regulation function, and a transmission method, capable of improving resolution of a pre-emphasis amount without increasing power consumption or a circuit area, in which the output buffer circuit 10 has a function which includes a delay circuit 23, an inverter 22 and output buffers 3 to 7 to transmit a logical signal to a transmission line 2 and generate a waveform having four or more types of signal voltages on a transmission side according to a signal attenuation amount of the transmission line 2 and the output buffer 3 has a variable resistance portion 12 at an on-resistance to change a pre-emphasis amount according to a change in a variable resistance value. The output buffer 3 has a selector 20 on a forward stage and a variable resistance portion 12 at an on-resistance. The inverter 22 is configured to select a signal to be input into the output buffer 6 according to a selector logic, invert a data signal and adjust a tap pre-emphasis amount by a select signal of the selector logic.

摘要翻译： 输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路以及传输方法，能够提高预加重量的分辨率而不增加功耗或电路面积，其中 输出缓冲电路10具有包括延迟电路23，反相器22和输出缓冲器3〜7的功能，以将逻辑信号发送到传输线2，并在发送侧产生具有四种或更多种信号电压的波形 根据传输线2的信号衰减量，输出缓冲器3具有导通电阻的可变电阻部分12，以根据可变电阻值的变化改变预加重量。 输出缓冲器3具有前级上的选择器20和导通电阻的可变电阻部分12。 反相器22被配置为根据选择器逻辑选择要输入到输出缓冲器6的信号，反转数据信号，并通过选择器逻辑的选择信号来调整抽头预加重量。

公开(公告)号：US20090085688A1

公开(公告)日：2009-04-02

申请号：US12145829

申请日：2008-06-25

申请人： Keiichi YAMAMOTO ,  Norio Chujo ,  Toru Yazaki ,  Hisaaki Kanai

发明人： Keiichi YAMAMOTO ,  Norio Chujo ,  Toru Yazaki ,  Hisaaki Kanai

IPC分类号： H03H11/30

CPC分类号： H03F3/3028 ,  H01L2924/19051 ,  H03F1/308 ,  H03F2200/447 ,  H03F2200/453 ,  H03K19/017581

摘要： In a semiconductor circuit, an impedance adjustment circuit having the characteristics same as those of a circuit having the nonlinear resistance characteristics is configured to include an operating point calculation circuit automatically calculating an operating point with a reference resistance through feedback control, and an impedance calculation circuit calculating the impedance at the operating point found by the operating point calculation circuit. The impedance adjustment circuit is also provided with an impedance determination circuit that determines whether or not the impedance found by the impedance calculation circuit is in a predetermined range. These components, i.e., the operating point calculation circuit, the impedance calculation circuit, and the impedance determination circuit, are provided each two for High-side and Low-side impedance adjustment use.

摘要翻译： 在半导体电路中，具有与具有非线性电阻特性的电路相同特性的阻抗调整电路被配置为包括工作点计算电路，通过反馈控制自动计算具有参考电阻的工作点，以及阻抗计算电路 计算由工作点计算电路找到的工作点处的阻抗。 阻抗调整电路还设置有阻抗确定电路，其确定由阻抗计算电路发现的阻抗是否在预定范围内。 这两个部件，即工作点计算电路，阻抗计算电路和阻抗确定电路，每两​​个用于高侧和低侧阻抗调节。

公开(公告)号：US07902860B2

公开(公告)日：2011-03-08

申请号：US12145829

申请日：2008-06-25

申请人： Keiichi Yamamoto ,  Norio Chujo ,  Toru Yazaki ,  Hisaaki Kanai

发明人： Keiichi Yamamoto ,  Norio Chujo ,  Toru Yazaki ,  Hisaaki Kanai

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03F3/3028 ,  H01L2924/19051 ,  H03F1/308 ,  H03F2200/447 ,  H03F2200/453 ,  H03K19/017581

摘要： In a semiconductor circuit, an impedance adjustment circuit having the characteristics same as those of a circuit having the nonlinear resistance characteristics is configured to include an operating point calculation circuit automatically calculating an operating point with a reference resistance through feedback control, and an impedance calculation circuit calculating the impedance at the operating point found by the operating point calculation circuit. The impedance adjustment circuit is also provided with an impedance determination circuit that determines whether or not the impedance found by the impedance calculation circuit is in a predetermined range. These components, i.e., the operating point calculation circuit, the impedance calculation circuit, and the impedance determination circuit, are provided each two for High-side and Low-side impedance adjustment use.

摘要翻译： 在半导体电路中，具有与具有非线性电阻特性的电路相同特性的阻抗调整电路被配置为包括工作点计算电路，通过反馈控制自动计算具有参考电阻的工作点，以及阻抗计算电路 计算由工作点计算电路找到的工作点处的阻抗。 阻抗调整电路还设置有阻抗确定电路，其确定由阻抗计算电路发现的阻抗是否在预定范围内。 这两个部件，即工作点计算电路，阻抗计算电路和阻抗确定电路，每两​​个用于高侧和低侧阻抗调节。

公开(公告)号：US07772877B2

公开(公告)日：2010-08-10

申请号：US12343521

申请日：2008-12-24

申请人： Norio Chujo ,  Keiichi Yamamoto ,  Hisaaki Kanai ,  Toru Yazaki

发明人： Norio Chujo ,  Keiichi Yamamoto ,  Hisaaki Kanai ,  Toru Yazaki

IPC分类号： H03K19/003

CPC分类号： H04L25/0278 ,  H04L25/028

摘要： An output buffer circuit, a differential output buffer circuit, an output buffer circuit having a regulation circuit and a regulation function, and a transmission method, to improve resolution of a pre-emphasis amount without increasing power consumption or a circuit area. The output buffer includes a delay circuit, an inverter and output buffers to transmit a logical signal to a transmission line and generate a waveform having four or more types of signal voltages on a transmission side according to a signal attenuation amount of the transmission line. The output buffer has a selector and a variable resistance portion at an output resistance to change a pre-emphasis amount according to a change in a variable resistance value. The inverter is configured to select a signal to input into the output buffer, invert a data signal and adjust a tap pre-emphasis amount by a select signal of the selector logic.

摘要翻译： 输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路以及传输方法，以提高预加重量的分辨率，而不增加功耗或电路面积。 输出缓冲器包括延迟电路，反相器和输出缓冲器，以将逻辑信号传输到传输线，并根据传输线的信号衰减量产生在发送侧具有四种或更多种类型的信号电压的波形。 输出缓冲器具有输出电阻的选择器和可变电阻部分，以根据可变电阻值的变化改变预加重量。 逆变器被配置为选择要输入到输出缓冲器的信号，反转数据信号并通过选择器逻辑的选择信号调整抽头预加重量。

公开(公告)号：US07965765B2

公开(公告)日：2011-06-21

申请号：US11965783

申请日：2007-12-28

申请人： Hisaaki Kanai ,  Norio Chujo ,  Masayoshi Yagyu

发明人： Hisaaki Kanai ,  Norio Chujo ,  Masayoshi Yagyu

IPC分类号： H03H7/30

CPC分类号： H04L25/03885

摘要： In an adjustment method of waveform equalization coefficient, one of jitter and amplitude is measured only in a case of an arbitrary signal sequence and a waveform equalization coefficient is adjusted. Particularly, using a signal of received signals other than a 010 signal or a 101 signal, code inversion time is measured. Since the code inversion time in a case where such signals are used becomes steeper in comparison with that in the conventional technique, adjustment time of the waveform equalization coefficient can be reduced.

摘要翻译： 在波形均衡系数的调整方法中，仅在任意信号序列的情况下测量抖动和幅度之一并且调整波形均衡系数。 特别地，使用除010信号或101信号之外的接收信号的信号，测量码反转时间。 由于在使用这种信号的情况下的代码反转时间与传统技术相比变得更陡峭，所以可以减小波形均衡系数的调整时间。

公开(公告)号：US20070184687A1

公开(公告)日：2007-08-09

申请号：US11657462

申请日：2007-01-25

申请人： Hisaaki Kanai ,  Norio Chujo ,  Masayoshi Yagyu

发明人： Hisaaki Kanai ,  Norio Chujo ,  Masayoshi Yagyu

IPC分类号： H05K1/00

CPC分类号： H05K1/0268 ,  H05K1/0237 ,  H05K3/0047 ,  H05K3/429 ,  H05K2203/0207 ,  H05K2203/0242 ,  H05K2203/163 ,  H05K2203/175

摘要： One of a group which is located on the side of a main surface of the circuit board than the one conductive layer of the plurality of conductive layers is used as a terminal to detect the digging depth of the through hole, and the digging of the through hole is stopped according to the change of the conductive state between the detection terminal and the through hole (or the one conductive layer which is electrically connected to this). A circuit board is formed so that the detection terminal in a group of the plurality of conductive layers contacts with the drill which dig the through hole and a group of the conductive layers except the detection terminal does not contact with the drill, respectively.

摘要翻译： 使用位于电路板的主表面侧的多个导电层的一个导电层中的一个作为端子来检测通孔的挖掘深度，并且挖掘通孔 根据检测端子和通孔（或与其电连接的一个导电层）之间的导电状态的变化来停止孔。 形成电路板，使得多个导电层中的一组中的检测端子与钻孔相接触，钻头分别钻出通孔，除了检测端子之外的一组导电层不与钻头接触。

公开(公告)号：US20080159460A1

公开(公告)日：2008-07-03

申请号：US11965783

申请日：2007-12-28

申请人： Hisaaki Kanai ,  Norio Chujo ,  Masayoshi Yagyu

发明人： Hisaaki Kanai ,  Norio Chujo ,  Masayoshi Yagyu

IPC分类号： H03D3/24

CPC分类号： H04L25/03885

摘要： In an adjustment method of waveform equalization coefficient, one of jitter and amplitude is measured only in a case of an arbitrary signal sequence and a waveform equalization coefficient is adjusted. Particularly, using a signal of received signals other than a 010 signal or a 101 signal, code inversion time is measured. Since the code inversion time in a case where such signals are used becomes steeper in comparison with that in the conventional technique, adjustment time of the waveform equalization coefficient can be reduced.

摘要翻译： 在波形均衡系数的调整方法中，仅在任意信号序列的情况下测量抖动和幅度之一并且调整波形均衡系数。 特别地，使用除010信号或101信号之外的接收信号的信号，测量码反转时间。 由于在使用这种信号的情况下的代码反转时间与传统技术相比变得更陡峭，所以可以减小波形均衡系数的调整时间。

公开(公告)号：US07969751B2

公开(公告)日：2011-06-28

申请号：US12216737

申请日：2008-07-10

申请人： Keiichi Yamamoto ,  Norio Chujo ,  Takashi Kumakura ,  Yosuke Ishimatsu

发明人： Keiichi Yamamoto ,  Norio Chujo ,  Takashi Kumakura ,  Yosuke Ishimatsu

IPC分类号： H02B1/26

CPC分类号： H05K7/1458 ,  G06F1/185

摘要： A high-speed signal transmission apparatus comprises: a housing; a plurality of daughter boards juxtaposed to one another in the housing; board-side connectors each provided on corresponding each of the juxtaposed daughter boards; and cable-side connectors fixed in the housing; wherein each of the board-side connectors is insertable/removable into/from corresponding each of the cable-side connectors, and wherein a cable group whose impedance matching can be achieved makes connection between the predetermined cable-side connectors.

摘要翻译： 高速信号传输装置包括：壳体; 多个子板在壳体中彼此并置; 每个并置的子板上设置的板侧连接器; 和固定在壳体中的电缆侧连接器; 其中每个电路板侧连接器可插入/移除相应的每个电缆侧连接器，并且其中可实现阻抗匹配的电缆组在预定电缆侧连接器之间进行连接。

公开(公告)号：US20080036512A1

公开(公告)日：2008-02-14

申请号：US11834714

申请日：2007-08-07

申请人： Keiichi Yamamoto ,  Norio Chujo

发明人： Keiichi Yamamoto ,  Norio Chujo

IPC分类号： H03K5/14 ,  H03H11/26 ,  H03K3/03

CPC分类号： H03H11/265 ,  H03K5/133 ,  H03K2005/0013

摘要： A signal delay circuit includes: a first inverter circuit; a second inverter circuit connected to an output terminal of the first inverter; and a feedback circuit extending from an output terminal of the second inverter to its input terminal. A delay time of the first inverter circuit is adjusted by controlling the amount of feedback through the feedback circuit. Here, the feedback circuit is formed by MOS transistors and the delay time is adjusted by controlling the gate voltages of the MOS transistors. The feedback amount is adjusted in relation to a variation in a power supply voltage and a variation in the delay time of the signal delay circuit is suppressed.

摘要翻译： 信号延迟电路包括：第一反相器电路; 连接到第一反相器的输出端的第二反相器电路; 以及从第二反相器的输出端子延伸到其输入端子的反馈电路。 通过控制通过反馈电路的反馈量来调节第一反相器电路的延迟时间。 这里，反馈电路由MOS晶体管形成，并且通过控制MOS晶体管的栅极电压来调整延迟时间。 相对于电源电压的变化来调整反馈量，抑制了信号延迟电路的延迟时间的变化。

公开(公告)号：US06979810B2

公开(公告)日：2005-12-27

申请号：US09930806

申请日：2001-08-15

申请人： Norio Chujo ,  Keiichi Yamamoto ,  Akio Osaki ,  Katsunori Hirano ,  Takayuki Nakao ,  Tomoaki Shimotsu ,  Atsushi Hasegawa ,  Tetsuya Aoki ,  Takeshi Yamashita

发明人： Norio Chujo ,  Keiichi Yamamoto ,  Akio Osaki ,  Katsunori Hirano ,  Takayuki Nakao ,  Tomoaki Shimotsu ,  Atsushi Hasegawa ,  Tetsuya Aoki ,  Takeshi Yamashita

IPC分类号： H01L31/10 ,  H01L31/107 ,  H03L7/085 ,  H03L7/091 ,  H04B10/07 ,  H04B10/2507 ,  H04B10/40 ,  H04B10/50 ,  H04B10/60 ,  H04L7/033 ,  H01J40/14 ,  H03D3/24 ,  H04B10/06

CPC分类号： H04L7/033 ,  H03L7/091

摘要： A sample & hold type phase detector is used in a CDR IC and, in jitter transfer bandwidth adjustment, VCO output waveforms 90° out of phase with each other can be inputted to the phase detector, whereby a jitter transfer bandwidth can be calculated by only the measurement of frequency and of a DC voltage and it is possible to make a jitter transfer bandwidth adjustment in DC test for IC.

摘要翻译： 在CDR IC中使用采样保持型相位检测器，并且在抖动传输带宽调整中，彼此相位差90°的VCO输出波形可以被输入到相位检测器，由此抖动传输带宽可以仅通过 频率和直流电压的测量，可以在IC的直流测试中进行抖动传输带宽调整。