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    Semiconductor device and manufacturing method for same
    1.
    发明授权
    Semiconductor device and manufacturing method for same 有权
    半导体器件及其制造方法相同

    公开(公告)号：US09136378B2

    公开(公告)日：2015-09-15

    申请号：US13824380

    申请日：2011-09-15

    申请人： Keiji Okumura ,  Mineo Miura ,  Katsuhisa Nagao ,  Shuhei Mitani

    发明人： Keiji Okumura ,  Mineo Miura ,  Katsuhisa Nagao ,  Shuhei Mitani

    IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/04 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/45 ,  H01L29/51

    CPC分类号： H01L29/7827 ,  H01L21/046 ,  H01L21/049 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/45 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7802 ,  H01L29/7811

    摘要： A semiconductor device includes a first conductive-type semiconductor layer, a second conductive-type body region formed in a surficial portion of the semiconductor layer, a first conductive-type source region formed in a surficial portion of the body region, a gate insulating film provided on the semiconductor layer and containing nitrogen atoms, the gate insulating film including a first portion in contact with the semiconductor layer outside the body region, a second portion in contact with the body region, and a third portion in contact with the source region, and a gate electrode provided on the gate insulating film in an area extending across the semiconductor layer outside the body region, the body region, and the source region. The third portion of the gate insulating film has a thickness greater than the thickness of the first portion and the thickness of the second portion.

    摘要翻译： 半导体器件包括第一导电类型半导体层，形成在半导体层的表面部分中的第二导电型体区域，形成在体区的表面部分中的第一导电型源极区域，栅极绝缘膜 设置在所述半导体层上并且含有氮原子的栅极绝缘膜，所述栅极绝缘膜包括与所述体区域外部的所述半导体层接触的第一部分，与所述主体区域接触的第二部分和与所述源极区域接触的第三部分， 以及栅极电极，设置在栅极绝缘膜上的延伸穿过体区，身体区域和源区域之外的半导体层的区域中。 栅极绝缘膜的第三部分的厚度大于第一部分的厚度和第二部分的厚度。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20130248981A1

    公开(公告)日：2013-09-26

    申请号：US13824380

    申请日：2011-09-15

    申请人： Keiji Okumura ,  Mineo Miura ,  Katsuhisa Nagao ,  Shuhei Mitani

    发明人： Keiji Okumura ,  Mineo Miura ,  Katsuhisa Nagao ,  Shuhei Mitani

    IPC分类号： H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/7827 ,  H01L21/046 ,  H01L21/049 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/45 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7802 ,  H01L29/7811

    摘要： A semiconductor device includes a first conductive-type semiconductor layer, a second conductive-type body region formed in a surficial portion of the semiconductor layer, a first conductive-type source region formed in a surficial portion of the body region, a gate insulating film provided on the semiconductor layer and containing nitrogen atoms, the gate insulating film including a first portion in contact with the semiconductor layer outside the body region, a second portion in contact with the body region, and a third portion in contact with the source region, and a gate electrode provided on the gate insulating film in an area extending across the semiconductor layer outside the body region, the body region, and the source region. The third portion of the gate insulating film has a thickness greater than the thickness of the first portion and the thickness of the second portion.

    摘要翻译： 半导体器件包括第一导电类型半导体层，形成在半导体层的表面部分中的第二导电型体区域，形成在体区的表面部分中的第一导电型源极区域，栅极绝缘膜 设置在所述半导体层上并且含有氮原子的栅极绝缘膜，所述栅极绝缘膜包括与所述体区域外部的所述半导体层接触的第一部分，与所述主体区域接触的第二部分和与所述源极区域接触的第三部分， 以及栅极电极，设置在栅极绝缘膜上的延伸穿过体区，身体区域和源区域之外的半导体层的区域中。 栅极绝缘膜的第三部分的厚度大于第一部分的厚度和第二部分的厚度。

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08546814B2

    公开(公告)日：2013-10-01

    申请号：US13258452

    申请日：2010-03-23

    申请人： Yuki Nakano ,  Shuhei Mitani ,  Mineo Miura

    发明人： Yuki Nakano ,  Shuhei Mitani ,  Mineo Miura

    IPC分类号： H01L31/0312

    CPC分类号： H01L29/7816 ,  H01L29/045 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7811 ,  H01L29/7813

    摘要： A semiconductor device including a semiconductor layer of a first conductivity type; a plurality of body regions of a second conductivity type, each formed in a region extending from the surface of the semiconductor layer to a halfway portion of the same in the thickness direction, and each spaced apart from each other in a direction perpendicular to the thickness direction; source regions of the first conductivity type, each formed on the surface layer part of each body region and spaced away from the edges of each body region; a gate insulating film formed on the semiconductor layer; and gate electrodes formed on the gate insulating film. In the semiconductor layer, trenches extending between two neighboring source regions are formed by digging from the source of the semiconductor layer, the inside surface of the trenches are covered by the gate insulating film, and the gate electrodes comprise surface-facing parts, which face the surface of the semiconductor layer, and buried parts, which are buried in the trenches.

    摘要翻译： 一种半导体器件，包括第一导电类型的半导体层; 多个第二导电类型的主体区域，各自形成在从半导体层的表面延伸到其厚度方向的中间部分的区域中，并且在垂直于厚度的方向上彼此间隔开 方向; 源区域，每个源区域形成在每个体区域的表面层部分上并与每个身体区域的边缘隔开; 形成在所述半导体层上的栅极绝缘膜; 以及形成在栅极绝缘膜上的栅电极。 在半导体层中，通过从半导体层的源进行挖掘来形成在两个相邻的源极区之间延伸的沟槽，沟槽的内表面被栅极绝缘膜覆盖，并且栅电极包括面向表面的部分 半导体层的表面和埋在沟槽中的埋藏部分。

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20120012861A1

    公开(公告)日：2012-01-19

    申请号：US13258452

    申请日：2010-03-23

    申请人： Yuki Nakano ,  Shuhei Mitani ,  Mineo Miura

    发明人： Yuki Nakano ,  Shuhei Mitani ,  Mineo Miura

    IPC分类号： H01L29/24

    CPC分类号： H01L29/7816 ,  H01L29/045 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7811 ,  H01L29/7813

    摘要： A semiconductor device including a semiconductor layer of a first conductivity type; a plurality of body regions of a second conductivity type, each formed in a region extending from the surface of the semiconductor layer to a halfway portion of the same in the thickness direction, and each spaced apart from each other in a direction perpendicular to the thickness direction; source regions of the first conductivity type, each formed on the surface layer part of each body region and spaced away from the edges of each body region; a gate insulating film formed on the semiconductor layer; and gate electrodes formed on the gate insulating film. In the semiconductor layer, trenches extending between two neighboring source regions are formed by digging from the source of the semiconductor layer, the inside surface of the trenches are covered by the gate insulating film, and the gate electrodes comprise surface-facing parts, which face the surface of the semiconductor layer, and buried parts, which are buried in the trenches.

    摘要翻译： 一种半导体器件，包括第一导电类型的半导体层; 多个第二导电类型的主体区域，各自形成在从半导体层的表面延伸到其厚度方向的中间部分的区域中，并且在垂直于厚度的方向上彼此间隔开 方向; 源区域，每个源区域形成在每个体区域的表面层部分上并与每个身体区域的边缘隔开; 形成在所述半导体层上的栅极绝缘膜; 以及形成在栅极绝缘膜上的栅电极。 在半导体层中，通过从半导体层的源进行挖掘来形成在两个相邻的源极区之间延伸的沟槽，沟槽的内表面被栅极绝缘膜覆盖，并且栅电极包括面向表面的部分 半导体层的表面和埋在沟槽中的埋藏部分。

    SiC semiconductor device
    5.
    发明授权
    SiC semiconductor device 有权
    SiC半导体器件

    公开(公告)号：US09159846B2

    公开(公告)日：2015-10-13

    申请号：US13314268

    申请日：2011-12-08

    申请人： Shuhei Mitani ,  Masatoshi Aketa

    发明人： Shuhei Mitani ,  Masatoshi Aketa

    IPC分类号： H01L29/872 ,  H01L29/06 ,  H01L29/16

    CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/1608 ,  H01L2224/04042 ,  H01L2224/05567 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/00 ,  H01L2224/05552

    摘要： A SiC semiconductor device includes a SiC semiconductor layer having a first-conductivity-type impurity, a field insulation film formed on a front surface of the SiC semiconductor layer and provided with an opening for exposing therethrough the front surface of the SiC semiconductor layer, an electrode connected to the SiC semiconductor layer through the opening of the field insulation film, and a guard ring having a second-conductivity-type impurity and being formed in a surface layer portion of the SiC semiconductor layer to make contact with a terminal end portion of the electrode connected to the SiC semiconductor layer. A second-conductivity-type impurity concentration in a surface layer portion of the guard ring making contact with the electrode is smaller than a first-conductivity-type impurity concentration in the SiC semiconductor layer.

    摘要翻译： SiC半导体器件包括具有第一导电类型杂质的SiC半导体层，形成在SiC半导体层的前表面上并且具有用于暴露于其中的SiC半导体层的前表面的开口的场绝缘膜， 通过场绝缘膜的开口与SiC半导体层连接的电极，以及具有第二导电型杂质的保护环，并形成在SiC半导体层的表层部分中，以与SiC半导体层的末端部分接触 所述电极连接到所述SiC半导体层。 与该电极接触的保护环的表层部的第二导电型杂质浓度小于SiC半导体层的第一导电型杂质浓度。

    Semiconductor Device
    8.
    发明申请
    Semiconductor Device 审中-公开
    半导体器件

    公开(公告)号：US20110012132A1

    公开(公告)日：2011-01-20

    申请号：US12866528

    申请日：2009-02-06

    申请人： Takukazu Otsuka ,  Shuhei Mitani

    发明人： Takukazu Otsuka ,  Shuhei Mitani

    IPC分类号： H01L29/24

    CPC分类号： H01L29/7802 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395

    摘要： Provided is a semiconductor device which has improved withstand voltage and can be manufactured by simpler manufacturing process. The semiconductor device according to the present invention includes: a SiC-containing n-type epitaxial layer 1 which is stacked on a surface of the n+-type substrate 11 containing SiC; n+-type source regions 5 arranged away from each other in a surface layer of the epitaxial layer 1; a p-type well contact region 2 sandwiched by the source regions 5; a p-type well region 3 arranged in contact with surfaces of the source regions 5 and p-type well contact region 2 on the substrate 11 side; and p-type well extension regions 4 arranged to sandwich the source regions 5 and p-type well region 3. The impurity concentration of the p-type well region 3 has a peak concentration at a position deeper in the depth direction from the surface of the epitaxial layer 1 toward the substrate 11 than the position of a peak concentration of the p-type well extension regions 4.

    摘要翻译： 提供了具有改善的耐受电压并且可以通过更简单的制造工艺制造的半导体器件。 根据本发明的半导体器件包括：层叠在包含SiC的n +型衬底11的表面上的含SiC的n型外延层1; 在外延层1的表面层中彼此远离配置的n +型源极区域5; 由源极区域5夹持的p型阱接触区域2; 与基板11侧的源极区域5和p型阱接触区域2的表面配置的p型阱区域3。 以及p型阱延伸区域4，其被布置成夹持源极区域5和p型阱区域3. p型阱区域3的杂质浓度在距离表面的深度方向上更深的位置具有峰值浓度 外延层1相对于p型阱延伸区域4的峰值浓度的位置朝向衬底11。