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    Semiconductor Device
    1.
    发明申请
    Semiconductor Device 审中-公开
    半导体器件

    公开(公告)号：US20110012132A1

    公开(公告)日：2011-01-20

    申请号：US12866528

    申请日：2009-02-06

    申请人： Takukazu Otsuka ,  Shuhei Mitani

    发明人： Takukazu Otsuka ,  Shuhei Mitani

    IPC分类号： H01L29/24

    CPC分类号： H01L29/7802 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395

    摘要： Provided is a semiconductor device which has improved withstand voltage and can be manufactured by simpler manufacturing process. The semiconductor device according to the present invention includes: a SiC-containing n-type epitaxial layer 1 which is stacked on a surface of the n+-type substrate 11 containing SiC; n+-type source regions 5 arranged away from each other in a surface layer of the epitaxial layer 1; a p-type well contact region 2 sandwiched by the source regions 5; a p-type well region 3 arranged in contact with surfaces of the source regions 5 and p-type well contact region 2 on the substrate 11 side; and p-type well extension regions 4 arranged to sandwich the source regions 5 and p-type well region 3. The impurity concentration of the p-type well region 3 has a peak concentration at a position deeper in the depth direction from the surface of the epitaxial layer 1 toward the substrate 11 than the position of a peak concentration of the p-type well extension regions 4.

    摘要翻译： 提供了具有改善的耐受电压并且可以通过更简单的制造工艺制造的半导体器件。 根据本发明的半导体器件包括：层叠在包含SiC的n +型衬底11的表面上的含SiC的n型外延层1; 在外延层1的表面层中彼此远离配置的n +型源极区域5; 由源极区域5夹持的p型阱接触区域2; 与基板11侧的源极区域5和p型阱接触区域2的表面配置的p型阱区域3。 以及p型阱延伸区域4，其被布置成夹持源极区域5和p型阱区域3. p型阱区域3的杂质浓度在距离表面的深度方向上更深的位置具有峰值浓度 外延层1相对于p型阱延伸区域4的峰值浓度的位置朝向衬底11。

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE 有权
    半导体器件和半导体器件的制造方法

    公开(公告)号：US20110079792A1

    公开(公告)日：2011-04-07

    申请号：US12876614

    申请日：2010-09-07

    申请人： Alexander B. Lostetter ,  Jared Hornberger ,  Takukazu Otsuka

    发明人： Alexander B. Lostetter ,  Jared Hornberger ,  Takukazu Otsuka

    IPC分类号： H01L29/78 ,  H01L21/84

    CPC分类号： H01L21/84 ,  H01L21/0485 ,  H01L21/6715 ,  H01L24/24 ,  H01L29/66068 ,  H01L2224/24998 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

    摘要： Provided are a semiconductor device and a method of fabricating the semiconductor device, the semiconductor device including: a source trace, a drain trace, and a gate trace placed on a substrate; a transistor which is placed on the drain trace and includes a source pad and a gate pad; insulating films placed between the drain and source traces and between the drain and gate traces on the substrate so as to cover sidewall surfaces of the transistor; a source spray electrode which is placed on the insulating film between the source and drain traces and connects the source pad of the transistor and the source trace; and a gate spray electrode placed on the insulating film between the gate and drain traces and connects the gate pad of the transistor and the gate trace.

    摘要翻译： 提供半导体器件和制造半导体器件的方法，该半导体器件包括：源极迹线，漏极迹线和置于衬底上的栅极迹线; 放置在漏极迹线上并包括源极焊盘和栅极焊盘的晶体管; 绝缘膜放置在漏极和源极之间以及衬底上的漏极和栅极迹线之间，以覆盖晶体管的侧壁表面; 源极喷射电极，放置在源极和漏极迹线之间的绝缘膜上，并连接晶体管的源极焊盘和源极迹线; 以及栅极喷射电极，其放置在栅极和漏极迹线之间的绝缘膜上，并连接晶体管的栅极焊盘和栅极迹线。

    Power Module
    10.
    发明申请
    Power Module 失效
    电源模块

    公开(公告)号：US20090095979A1

    公开(公告)日：2009-04-16

    申请号：US12243098

    申请日：2008-10-01

    申请人： Masao Saito ,  Takukazu Otsuka ,  Keiji Okumura

    发明人： Masao Saito ,  Takukazu Otsuka ,  Keiji Okumura

    IPC分类号： H01L23/34 ,  H01L29/739

    CPC分类号： H01L25/18 ,  H01L23/3675 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A power module includes a substrate having first and second main substrate surfaces; a semiconductor device disposed on the first main substrate surface, and having a first main surface on which a first main electrode is formed, and a second main surface on which a second main electrode in contact with the first main substrate surface is formed; a heat conduction portion disposed on the first main substrate surface in a residual region of a region on which the semiconductor device is disposed; and an upper cooling portion disposed on the heat conduction portion.

    摘要翻译： 功率模块包括具有第一和第二主衬底表面的衬底; 半导体器件，其设置在所述第一主衬底表面上，并且具有形成有第一主电极的第一主表面和形成有与所述第一主衬底表面接触的第二主电极的第二主表面; 在设置有半导体器件的区域的残留区域中的第一主衬底表面上设置的热传导部分; 以及设置在导热部上的上部冷却部。