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    NONVOLATILE MEMORY ELEMENT AND NONVOLATILE MEMORY DEVICE
    3.
    发明申请
    NONVOLATILE MEMORY ELEMENT AND NONVOLATILE MEMORY DEVICE 有权
    非易失性存储元件和非易失性存储器件

    公开(公告)号：US20140061579A1

    公开(公告)日：2014-03-06

    申请号：US13995383

    申请日：2012-10-22

    申请人： Zhiqiang Wei ,  Takeshi Takagi ,  Koji Katayama

    发明人： Zhiqiang Wei ,  Takeshi Takagi ,  Koji Katayama

    IPC分类号： H01L45/00 ,  H01L27/24

    CPC分类号： H01L45/145 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/15 ,  H01L27/101 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1625

    摘要： A variable resistance nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer including: a first oxide layer including a metal oxide having non-stoichiometric composition and including p-type carriers; a second oxide layer located between and in contact with the first oxide layer and a second electrode and including a metal oxide having non-stoichiometric composition and including n-type carriers; an oxygen reservoir region located in the first oxide layer, having no contact with the first electrode, and having an oxygen content atomic percentage higher than that of the first oxide layer; and a local region located in the second oxide layer, having contact with the oxygen reservoir region, and having an oxygen content atomic percentage lower than that of the second oxide layer.

    摘要翻译： 可变电阻非易失性存储元件包括第一电极，第二电极和可变电阻层，包括：包含具有非化学计量组成的金属氧化物并包括p型载流子的第一氧化物层; 位于第一氧化物层之间并与第一氧化物层接触的第二氧化物层和第二电极，并且包括具有非化学计量组成并包括n型载体的金属氧化物; 位于所述第一氧化物层中的与第一电极没有接触并且氧含量原子百分比高于第一氧化物层的氧储存区; 以及位于所述第二氧化物层中的与氧储存区接触并且氧含量原子百分比低于第二氧化物层的原子百分比的局部区域。

    Nonvolatile memory element and semiconductor memory device including nonvolatile memory element
    4.
    发明授权
    Nonvolatile memory element and semiconductor memory device including nonvolatile memory element 有权
    包括非易失性存储元件的非易失性存储元件和半导体存储器件

    公开(公告)号：US08339835B2

    公开(公告)日：2012-12-25

    申请号：US13000243

    申请日：2010-04-22

    申请人： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

    发明人： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

    IPC分类号： G11C11/00

    CPC分类号： H01L27/101 ,  G11C13/0002 ,  G11C2213/72 ,  H01L27/24

    摘要： A nonvolatile memory element includes a current controlling element having a non-linear current-voltage characteristic, a resistance variable element which changes reversibly between a low-resistance state and a high-resistance state in which a resistance value of the resistance variable element is higher than a resistance value of the resistance variable element in the low-resistance state, in response to voltage pulses applied, and a fuse. The current controlling element, the resistance variable element and the fuse are connected in series, and the fuse is configured to be blown when the current controlling element is substantially short-circuited.

    摘要翻译： 非易失性存储元件包括具有非线性电流 - 电压特性的电流控制元件，在电阻可变元件的电阻值较高的低电阻状态与高电阻状态之间可逆地改变的电阻可变元件 比电阻可变元件在低电阻状态下的电阻值，响应于施加的电压脉冲和保险丝。 电流控制元件，电阻可变元件和保险丝串联连接，并且当电流控制元件基本上短路时，保险丝被配置为被熔断。

    METHOD FOR MANUFACTURING NON-VOLATILE MEMORY DEVICE, NON-VOLATILE MEMORY ELEMENT, AND NON-VOLATILE MEMORY DEVICE
    5.
    发明申请
    METHOD FOR MANUFACTURING NON-VOLATILE MEMORY DEVICE, NON-VOLATILE MEMORY ELEMENT, AND NON-VOLATILE MEMORY DEVICE 有权
    用于制造非易失性存储器件，非易失性存储器元件和非易失性存储器件的方法

    公开(公告)号：US20120319072A1

    公开(公告)日：2012-12-20

    申请号：US13580401

    申请日：2011-02-23

    申请人： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

    发明人： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

    IPC分类号： H01L47/00 ,  H01L21/02

    CPC分类号： H01L45/1226 ,  G11C13/0002 ,  G11C2213/77 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1633

    摘要： A manufacturing method for manufacturing, with a simple process, a non-volatile memory apparatus having a stable memory performance includes: (a) forming a stacking-structure body above a substrate by alternately stacking conductive layers comprising a transition metal and interlayer insulating films comprising an insulating material; (b) forming a contact hole penetrating through the stacking-structure body to expose part of each of the conductive layers; (c) forming variable resistance layers by oxidizing the part of each of the conductive layers, the part being exposed in the contact hole, and each of the variable resistance layers having a resistance value that reversibly changes according to an application of an electric signal; and (d) forming a pillar electrode in the contact hole by embedding a conductive material in the contact hole, the pillar electrode being connected to each of the variable resistance layers.

    摘要翻译： 一种以简单的工艺制造具有稳定的存储性能的非易失性存储装置的制造方法包括：（a）通过交替堆叠包括过渡金属和层间绝缘膜的导电层，在衬底上形成堆叠结构体，所述导电层包括： 绝缘材料; （b）形成穿过堆叠结构体的接触孔，以暴露出每个导电层的部分; （c）通过氧化每个导电层的一部分形成可变电阻层，该部分暴露在接触孔中，并且每个可变电阻层具有根据电信号的应用可逆地改变的电阻值; 和（d）通过在接触孔中埋设导电材料而在接触孔中形成柱状电极，该柱状电极与各可变电阻层连接。

    Resistance variable nonvolatile memory device
    6.
    发明授权
    Resistance variable nonvolatile memory device 有权
    电阻变量非易失性存储器件

    公开(公告)号：US08320159B2

    公开(公告)日：2012-11-27

    申请号：US12993706

    申请日：2010-03-15

    申请人： Zhiqiang Wei ,  Ryotaro Azuma ,  Takeshi Takagi ,  Mitsuteru Iijima ,  Yoshihiko Kanzawa

    发明人： Zhiqiang Wei ,  Ryotaro Azuma ,  Takeshi Takagi ,  Mitsuteru Iijima ,  Yoshihiko Kanzawa

    IPC分类号： G11C11/00

    CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0038 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/115 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

    摘要： Each of memory cells (MC) includes one transistor and one resistance variable element. The transistor includes a first main terminal, a second main terminal and a control terminal. The resistance variable element includes a first electrode, a second electrode and a resistance variable layer provided between the first electrode and the second electrode. A first main terminal of one of two adjacent memory cells is connected to a second main terminal of the other memory cell, to form a series path (SP) sequentially connecting main terminals of the plurality of memory cells in series. Each of the memory cells is configured such that the control terminal is a part of a first wire (WL) associated with the memory cell or is connected to the first wire associated with the memory cell, the second electrode is a part of a second wire (SL) associated with the memory cell or is connected to the second wire associated with the memory cell; and the first electrode is a part of a series path (SP) associated with the memory cell or is connected to the series path associated with the memory cell.

    摘要翻译： 每个存储单元（MC）包括一个晶体管和一个电阻可变元件。 晶体管包括第一主端子，第二主端子和控制端子。 电阻可变元件包括设置在第一电极和第二电极之间的第一电极，第二电极和电阻变化层。 两个相邻存储单元之一的第一主端子连接到另一个存储单元的第二主端子，以形成串联连接多个存储单元的主端子的串行路径（SP）。 每个存储器单元被配置为使得控制端子是与存储器单元相关联的第一布线（WL）的一部分或者连接到与存储单元相关联的第一布线，第二电极是第二布线 （SL），或者连接到与存储器单元相关联的第二线; 并且第一电极是与存储器单元相关联的或连接到与存储器单元相关联的串联路径的串联路径（SP）的一部分。

    NONVOLATILE MEMORY ELEMENT, NONVOLATILE MEMORY APPARATUS, AND METHOD OF MANUFACTURE THEREOF
    8.
    发明申请
    NONVOLATILE MEMORY ELEMENT, NONVOLATILE MEMORY APPARATUS, AND METHOD OF MANUFACTURE THEREOF 有权
    非易失性存储元件，非易失性存储器件及其制造方法

    公开(公告)号：US20100200852A1

    公开(公告)日：2010-08-12

    申请号：US12709148

    申请日：2010-02-19

    申请人： Yoshio Kawashima ,  Takeshi Takagi ,  Takumi Mikawa ,  Zhiqiang Wei

    发明人： Yoshio Kawashima ,  Takeshi Takagi ,  Takumi Mikawa ,  Zhiqiang Wei

    IPC分类号： H01L29/68 ,  H01L21/34

    CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1658 ,  H01L45/1675

    摘要： A lower electrode layer 2, an upper electrode layer 4 formed above the lower electrode layer 2, and a metal oxide thin film layer 3 formed between the lower electrode layer 2 and the upper electrode layer 4 are provided. The metal oxide thin film layer 3 includes a first region 3a whose value of resistance increases or decreases by an electric pulse that is applied between the lower electrode layer 2 and the upper electrode layer 4 and a second region 3b arranged around the first region 3a and having a larger content of oxygen than the first region 3a, wherein the lower and upper electrode layers 2 and 4 and at least a part of the first region 3a are arranged so as to overlap as viewed from the direction of the thickness of the first region 3a.

    摘要翻译： 设置下电极层2，形成在下电极层2上的上电极层4和形成在下电极层2和上电极层4之间的金属氧化物薄膜层3。 金属氧化物薄膜层3包括第一区域3a，其第一区域3a的电阻值通过施加在下电极层2和上电极层4之间的电脉冲和围绕第一区域3a布置的第二区域3b而增大或减小，以及 具有比第一区域3a更大的氧含量，其中下电极层2和上电极层4以及第一区域3a的至少一部分从第一区域的厚度方向观察而重叠 3a。

    RESISTANCE VARIABLE MEMORY APPARATUS
    9.
    发明申请
    RESISTANCE VARIABLE MEMORY APPARATUS 有权
    电阻可变存储器

    公开(公告)号：US20100046270A1

    公开(公告)日：2010-02-25

    申请号：US12514025

    申请日：2007-11-16

    申请人： Yoshikazu Katoh ,  Kazuhiko Shimakawa ,  Zhiqiang Wei

    发明人： Yoshikazu Katoh ,  Kazuhiko Shimakawa ,  Zhiqiang Wei

    IPC分类号： G11C17/00 ,  G11C11/00

    CPC分类号： G11C13/003 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/76 ,  G11C2213/79

    摘要： A resistance variable memory apparatus (100) of the present invention is a resistance variable memory apparatus (100) using a resistance variable element (22) transitioning between plural resistance states in response to electric pulses of the same polarity, in which a series resistance setting unit (10) is configured to set a resistance value of the series current path and a parallel resistance setting unit (30) is configured to set a resistance value of a parallel current path such that the resistance values become resistance values at which a node potential is not larger than a second voltage level in a state where an electric pulse application device (50) is outputting a first electric pulse after the resistance variable element (22) has switched to the high-resistance state, and the node potential is not larger than a first voltage level in the state where the electric pulse application device (50) is outputting a second electric pulse after the resistance variable element (22) has switched to the low-resistance state.

    摘要翻译： 本发明的电阻可变存储装置（100）是电阻可变存储装置（100），其使用电阻可变元件（22），其响应于相同极性的电脉冲在多个电阻状态之间转变，其中串联电阻设定 单元（10）被配置为设置串联电流路径的电阻值，并联电阻设定单元（30）被配置为设置并联电流路径的电阻值，使得电阻值成为节点电位 在电阻可变元件（22）切换到高电阻状态之后电脉冲施加装置（50）输出第一电脉冲的状态下不大于第二电压电平，并且节点电位不大 在电脉冲施加装置（50）在电阻可变元件（22）之后输出第二电脉冲的状态下的第一电压电平ha s切换到低电阻状态。

    NONVOLATILE MEMORY ELEMENT AND NONVOLATILE MEMORY DEVICE
    10.
    发明申请
    NONVOLATILE MEMORY ELEMENT AND NONVOLATILE MEMORY DEVICE 有权
    非易失性存储元件和非易失性存储器件

    公开(公告)号：US20120327702A1

    公开(公告)日：2012-12-27

    申请号：US13599286

    申请日：2012-08-30

    申请人： Takeshi Takagi ,  Zhiqiang Wei ,  Takeki Ninomiya ,  Shunsaku Muraoka ,  Yoshihiko Kanzawa

    发明人： Takeshi Takagi ,  Zhiqiang Wei ,  Takeki Ninomiya ,  Shunsaku Muraoka ,  Yoshihiko Kanzawa

    IPC分类号： H01L45/00 ,  G11C11/21

    CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

    摘要： A nonvolatile memory element includes: a first electrode layer; a second electrode layer; and a variable resistance layer which is placed between the electrode layers, and whose resistance state reversibly changes between a high resistance state and a low resistance state based on a polarity of a voltage applied between the electrode layers. The variable resistance layer is formed by stacking a first oxide layer including an oxide of a first transition metal and a second oxide layer including an oxide of a second transition metal which is different from the first transition metal. At least one of the following conditions is satisfied: (1) a dielectric constant of the second oxide layer is larger than a dielectric constant of the first oxide layer; and (2) a band gap of the second oxide layer is smaller than a band gap of the first oxide layer.

    摘要翻译： 非易失性存储元件包括：第一电极层; 第二电极层; 以及可变电阻层，其设置在电极层之间，并且其电阻状态基于施加在电极层之间的电压的极性而在高电阻状态和低电阻状态之间可逆地变化。 可变电阻层通过堆叠包括第一过渡金属的氧化物的第一氧化物层和包含与第一过渡金属不同的第二过渡金属的氧化物的第二氧化物层而形成。 满足以下条件中的至少一个：（1）第二氧化物层的介电常数大于第一氧化物层的介电常数; 和（2）第二氧化物层的带隙小于第一氧化物层的带隙。