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    Methods for forming co-planar wafer-scale chip packages
    1.
    发明申请
    Methods for forming co-planar wafer-scale chip packages 有权
    用于形成共面晶片级芯片封装的方法

    公开(公告)号：US20060110851A1

    公开(公告)日：2006-05-25

    申请号：US10994494

    申请日：2004-11-20

    申请人： Lloyd Burrell ,  Howard Chen ,  Louis Hsu ,  Wolfgang Sauter

    发明人： Lloyd Burrell ,  Howard Chen ,  Louis Hsu ,  Wolfgang Sauter

    IPC分类号： H01L21/48 ,  H01L21/50

    CPC分类号： H01L23/5389 ,  H01L21/52 ,  H01L23/147 ,  H01L23/5385 ,  H01L2221/68322 ,  H01L2221/68345 ,  H01L2924/0002 ,  H01L2924/1433 ,  H01L2924/00

    摘要： Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.

    摘要翻译： 提出了用于形成共面多芯片晶片级封装的经济方法。 部分晶片接合和部分晶片切割技术用于制造芯片以及口袋。 然后将完成的芯片安装在载体基板的相应凹穴中，并且芯片之间的全局互连形成在成品芯片的顶部平坦表面上。 所提出的方法促进了用不同工艺步骤和材料制造的芯片的集成。 不需要使用诸如化学机械抛光剂的平面化处理来平坦化芯片的顶表面。 由于芯片精确地对准并且所有芯片都朝上安装，所以模块准备好进行全局布线，从而不需要将芯片从倒置的位置翻转。