公开(公告)号：US12086427B2

公开(公告)日：2024-09-10

申请号：US17677641

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Sriteja Yamparala ,  Fulvio Rori ,  Marco Domenico Tiburzi ,  Walter Di Francesco ,  Chiara Cerafogli ,  Tawalin Opastrakoon

IPC: G06F1/28 ,  G06F1/08 ,  G06F3/06

CPC classification number: G06F3/0625 ,  G06F1/08 ,  G06F1/28 ,  G06F3/0653 ,  G06F3/0673

Abstract: Various embodiments of the present disclosure relate to monitoring the integrity of power signals within memory systems. A method can include receiving a power signal at a memory component, and monitoring, via a power signal monitoring component of the memory component, an integrity characteristic of the power signal. Responsive to the integrity characteristic meeting a particular criteria, the method can include providing a status indication to a control component external to the memory component.

公开(公告)号：US11978680B2

公开(公告)日：2024-05-07

申请号：US17534973

申请日：2021-11-24

Applicant: Micron Technology, Inc.

Inventor： Kenneth William Marr ,  Chiara Cerafogli ,  Michele Piccardi ,  Marco-Domenico Tiburzi ,  Eric Higgins Freeman ,  Joshua Daniel Tomayer

IPC: H01L21/66 ,  G01B7/16 ,  G01L1/16 ,  G01L1/18 ,  H01L29/84

CPC classification number: H01L22/34 ,  G01B7/18 ,  G01L1/16 ,  G01L1/18 ,  H01L29/84

Abstract: A microelectronic chip device includes a semiconductor substrate and multiple on-chip strain sensors (OCSSs) constructed on the substrate at various locations of the substrate. The OCSSs may each include multiple piezoresistive devices configured to sense a strain at a location of the various locations and produce a strain signal representing the strain at that location. A strain measurement circuit may also be constructed on the semiconductor substrate and configured to measure strain parameters from the strain signals produced by the OCSSs. The strain parameters represent the strains at the various location. Values of the strain parameters can be used for analysis of mechanical stress on the chip device.

公开(公告)号：US20230367496A1

公开(公告)日：2023-11-16

申请号：US17663138

申请日：2022-05-12

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Carla L. Christensen ,  Iolanda Del Villano ,  Lalla Fatima Drissi ,  Anna Scalesse ,  Maddalena Calzolari

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for block repurposing based on health metrics are described. The method may involve setting a storage state of a block of memory cells, the storage state corresponding to a storage density of the block of memory cells or an access mode of the block of memory cells. Further, the method may involve updating the storage state of the block of memory cells based on a health condition associated with the block of memory cells and accessing the block of memory cells based on the updated storage state of the block of memory cells.

公开(公告)号：US20220277796A1

公开(公告)日：2022-09-01

申请号：US17747516

申请日：2022-05-18

Applicant: Micron Technology, Inc.

Inventor： Shannon Marissa Hansen ,  Fulvio Rori ,  Andrea D'Alessandro ,  Jason Lee Nevill ,  Chiara Cerafogli

IPC: G11C16/20 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G06F3/06

Abstract: A variety of applications can include a memory device designed to perform sensing of a memory cell of a string of memory cells using a modified shielded bit line sensing operation. The modified shielded bit line sensing operation includes pre-charging a data line corresponding to the string with the string enabled to couple to the data line. The modified shielded bit line sensing operation can be implemented in a hybrid initialization routine for the memory device. The hybrid initialization routine can include a sensing read routine corresponding to an all data line configuration of data lines of the memory device and a modified sensing read routine corresponding to a shielded data line configuration of the data lines with selected strings enabled during pre-charging. A read retry routine associated with the modified sensing read routine can be added to the hybrid initialization routine. Additional devices, systems, and methods are discussed.

公开(公告)号：US11424169B2

公开(公告)日：2022-08-23

申请号：US16535882

申请日：2019-08-08

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Kenneth William Marr ,  Brian J. Soderling ,  Michael P. Violette ,  Joshua Daniel Tomayer ,  James E. Davis

IPC: H01L23/528 ,  G11C16/26 ,  H01L21/66 ,  H01L23/00 ,  H01L27/11526 ,  H01L27/11573 ,  H03K3/03 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/04 ,  G11C29/14 ,  H01L27/11556

Abstract: Some embodiments include apparatuses and methods of fabricating the apparatuses. One of the apparatuses includes a substrate of a semiconductor die; a memory cell portion located over a first portion of the substrate; a conductive pad portion located over a second portion of the substrate and outside the memory cell portion; and a sensor circuit including a portion located over the second portion of the substrate and under the conductive pad portion. The conductive pad portion includes conductive pads. Each of the conductive pads is part of a respective electrical path coupled to a conductive contact of a base outside the substrate.

公开(公告)号：US11355200B2

公开(公告)日：2022-06-07

申请号：US16996363

申请日：2020-08-18

Applicant: Micron Technology, Inc.

Inventor： Shannon Marissa Hansen ,  Fulvio Rori ,  Andrea D'Alessandro ,  Jason Lee Nevill ,  Chiara Cerafogli

IPC: G11C16/20 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G06F3/06 ,  H01L27/11582 ,  H01L27/11556

Abstract: A variety of applications can include a memory device designed to perform sensing of a memory cell of a string of memory cells using a modified shielded bit line sensing operation. The modified shielded bit line sensing operation includes pre-charging a data line corresponding to the string with the string enabled to couple to the data line. The modified shielded bit line sensing operation can be implemented in a hybrid initialization routine for the memory device. The hybrid initialization routine can include a sensing read routine corresponding to an all data line configuration of data lines of the memory device and a modified sensing read routine corresponding to a shielded data line configuration of the data lines with selected strings enabled during pre-charging. A read retry routine associated with the modified sensing read routine can be added to the hybrid initialization routine. Additional devices, systems, and methods are discussed.

公开(公告)号：US20210342100A1

公开(公告)日：2021-11-04

申请号：US17373301

申请日：2021-07-12

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Fulvio Rori ,  Jonathan W. Oh ,  Giuseppe Cariello

IPC: G06F3/06 ,  G11C16/10 ,  G06F11/10 ,  G11C16/26 ,  G11C16/04 ,  G11C29/52

Abstract: Devices and techniques for NAND temperature-aware operations are disclosed herein. A device controller can receive a command to write data to a component in the device. A temperature corresponding to the component can be obtained in response to receiving the command. The command can be executed by the controller to write data to the component. Executing the command can include writing the temperature into a management portion of the device that is separate from a user portion of the device to which the data is written.

公开(公告)号：US20200211914A1

公开(公告)日：2020-07-02

申请号：US16294469

申请日：2019-03-06

Applicant: Micron Technology, Inc.

Inventor： Kenneth William Marr ,  Chiara Cerafogli ,  Michele Piccardi ,  Marco-Domenico Tiburzi ,  Eric Higgins Freeman ,  Joshua Daniel Tomayer

IPC: H01L21/66 ,  G01B7/16

Abstract: A microelectronic chip device includes a semiconductor substrate and multiple on-chip strain sensors (OCSS s) constructed on the substrate at various locations of the substrate. The OCSSs may each include multiple piezoresistive devices configured to sense a strain at a location of the various locations and produce a strain signal representing the strain at that location. A strain measurement circuit may also be constructed on the semiconductor substrate and configured to measure strain parameters from the strain signals produced by the OCSSs. The strain parameters represent the strains at the various location. Values of the strain parameters can be used for analysis of mechanical stress on the chip device.

公开(公告)号：US20240427507A1

公开(公告)日：2024-12-26

申请号：US18827515

申请日：2024-09-06

Applicant: Micron Technology, Inc.

Inventor： Sriteja Yamparala ,  Fulvio Rori ,  Marco Domenico Tiburzi ,  Walter Di Francesco ,  Chiara Cerafogli ,  Tawalin Opastrakoon

IPC: G06F3/06 ,  G06F1/08 ,  G06F1/28

Abstract: Various embodiments of the present disclosure relate to monitoring the integrity of power signals within memory systems. A method can include receiving a power signal at a memory component, and monitoring, via a power signal monitoring component of the memory component, an integrity characteristic of the power signal. Responsive to the integrity characteristic meeting a particular criteria, the method can include providing a status indication to a control component external to the memory component.

公开(公告)号：US11989443B2

公开(公告)日：2024-05-21

申请号：US17663139

申请日：2022-05-12

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Carla L. Christensen ,  Iolanda Del Villano ,  Lalla Fatima Drissi ,  Anna Scalesse ,  Maddalena Calzolari

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679

Abstract: Methods, systems, and devices for techniques for enhanced read performance on blocks of memory cells are described. The method may involve selecting a first block of memory cells from a set of blocks of memory cells of a memory system based on a condition of the first block of memory cells being met and setting one or more programming parameters corresponding to the first block of memory cells such that the one or more programming parameters are within a threshold value of one or more programming parameters corresponding to a second block associated with a storage density different from a storage density of the first block of memory cells. Further, the method may involve performing an operation on the block of memory cells according to the one or more programming parameters.