公开(公告)号：US20040159948A1

公开(公告)日：2004-08-19

申请号：US10782685

申请日：2004-02-19

Applicant: Micron Technology, Inc.

Inventor： Randhir P.S. Thakur

IPC: H01L029/00 ,  H01L021/4763 ,  H01L023/48 ,  H01L029/40

CPC classification number: H01L21/76831 ,  H01L21/28525 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76879 ,  H01L2924/0002 ,  Y10S257/915 ,  H01L2924/00

Abstract: A new method and structure for an improved contact using doped silicon is provided. The structures are integrated into several higher level embodiments. The improved contact has low contact resistivity. Improved junctions are thus provided between an IGFET device and subsequent metallization layers. The improvements are obtained through the use of a silicon-germanium (SinullGe) alloy. The alloy can be formed from depositing germanium onto the substrate and subsequently annealing the contact or by selectively depositing the preformed alloy into a contact opening. The above advantages are incorporated with relatively few process steps.

公开(公告)号：US20030001212A1

公开(公告)日：2003-01-02

申请号：US10231758

申请日：2002-08-29

Applicant: Micron Technology, Inc.

Inventor： Yongjun Hu ,  Randhir P.S. Thakur ,  Scott DeBoer

IPC: H01L029/76

CPC classification number: H01L21/28052 ,  H01L21/28061 ,  H01L27/10891 ,  H01L29/4941 ,  Y10S257/914 ,  Y10S257/915

Abstract: Methods and apparatus for forming word line stacks comprise forming a thin nitride layer coupled between a bottom silicon layer and a conductor layer. In a further embodiment, a diffusion barrier layer is coupled between the thin nitride layer and the bottom silicon layer. The thin nitride layer is formed by annealing a silicon oxide film in a nitrogen-containing ambient.

公开(公告)号：US20020187654A1

公开(公告)日：2002-12-12

申请号：US10213812

申请日：2002-08-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott J. DeBoer ,  Randhir P.S. Thakur

IPC: H01L021/31 ,  H01L021/469 ,  C23C016/00

CPC classification number: H01L21/02183 ,  C23C16/40 ,  C23C16/52 ,  H01L21/02274 ,  H01L21/02356 ,  H01L21/316 ,  H01L21/31691 ,  H01L28/40 ,  H01L29/516

Abstract: A method of forming a high dielectric oxide film conventionally formed using a post formation oxygen anneal to reduce the leakage current of such film includes forming a high dielectric oxide film on a surface. The high dielectric oxide film has a dielectric constant greater than about 4 and includes a plurality of oxygen vacancies present during the formation of the film. The high dielectric oxide film is exposed during the formation thereof to an amount of atomic oxygen sufficient for reducing the number of oxygen vacancies and eliminating the post formation oxygen anneal of the high dielectric oxide film. Further, the amount of atomic oxygen used in the formation method may be controlled as a function of the amount of oxygen incorporated into the high dielectric oxide film during the formation thereof or be controlled as a function of the concentration of atomic oxygen in a process chamber in which the high dielectric oxide film is being formed. An apparatus for forming the high dielectric oxide film is also described.

Abstract translation: 使用后形成氧退火形成常规形成的高电介质氧化膜以减少这种膜的漏电流的方法包括在表面上形成高介电氧化物膜。 高电介质氧化物膜具有大于约4的介电常数，并且在膜的形成期间包括存在的多个氧空位。 高电介质氧化物膜在其形成期间暴露于足以减少氧空位数并且消除高电介质氧化物膜的后形成氧退火的原子氧量。 另外，形成方法中使用的原子氧的量可以作为在形成高电介质氧化物膜期间掺入到高电介质氧化膜中的氧的量的函数来控制，或者作为处理室中的原子氧浓度的函数来控制 其中形成高电介质氧化膜。 还描述了用于形成高电介质氧化物膜的装置。

公开(公告)号：US20020067489A1

公开(公告)日：2002-06-06

申请号：US10057363

申请日：2001-10-29

Applicant: Micron Technology, Inc.

Inventor： Randhir P.S. Thakur ,  Michael Nuttall ,  J. Brett Rolfson ,  Robert James Burke

IPC: G01B011/00

CPC classification number: G01B11/303

Abstract: Disclosed is a process for analyzing the surface characteristics of opaque materials. The method comprises in one embodiment the use of a UV reflectometer to build a calibration matrix of data from a set of control samples and correlating a desired surface characteristic such as roughness or surface area to the set of reflectances of the control samples. The UV reflectometer is then used to measure the reflectances of a test sample of unknown surface characteristics. Reflectances are taken at a variety of angles of reflection for a variety of wavelengths, preferably between about 250 nanometers to about 400 nanometers. These reflectances are then compared against the reflectances of the calibration matrix in order to correlate the closest data in the calibration matrix. By so doing, a variety of information is thereby concluded, due to the broad spectrum of wavelengths and angles of reflection used. This includes information pertaining to the roughness and surface area, as well as other surface characteristics such as grain size, grain density, grain shape, and boundary size between the grains. Surface characteristic evaluation can be conducted in-process in a manner which is non-destructive to the test sample. The method is particularly useful for determining the capacitance of highly granular polysilicon test samples used in the construction of capacitator plates in integrated circuit technology, and can be used to determine the existence of flat smooth surfaces, and the presence of prismatic and hemispherical irregularities on flat smooth surfaces.

Abstract translation: 公开了一种用于分析不透明材料的表面特性的方法。 该方法在一个实施方案中包括使用UV反射计来构建来自一组对照样品的数据的校准矩阵，并将期望的表面特性如粗糙度或表面积与对照样品的一组反射率相关联。 然后使用UV反射计来测量未知表面特性的测试样品的反射率。 对于各种波长，优选在约250纳米到约400纳米之间的各种反射角拍摄反射率。 然后将这些反射率与校准矩阵的反射率进行比较，以便将校准矩阵中最接近的数据相关联。 通过这样做，由于广泛的波长和使用的反射角度，从而得出各种信息。 这包括关于粗糙度和表面积的信息，以及晶粒之间的其他表面特性，例如晶粒尺寸，晶粒密度，晶粒形状和边界尺寸。 表面特性评估可以以对测试样品非破坏性的方式进行。 该方法对于确定集成电路技术中电容器板结构中使用的高度粒状多晶硅测试样品的电容特别有用，可用于确定平坦光滑表面的存在，以及平面上存在棱镜和半球形不规则 光滑的表面。

公开(公告)号：US20040171244A1

公开(公告)日：2004-09-02

申请号：US10789890

申请日：2004-02-27

Applicant: Micron Technology, Inc.

Inventor： Klaus Florian Schuegraf ,  Scott Jeffrey DeBoer ,  Randhir P.S. Thakur

IPC: H01L021/336 ,  H01L021/3205 ,  H01L021/4763

CPC classification number: H01L29/6656 ,  H01L21/28247 ,  H01L21/31683 ,  H01L21/32 ,  Y10S257/90

Abstract: A method of forming an encapsulating spacer prior to gate stack reoxidation is provided which prevents the formation of undesirable metal oxides during reoxidation. A material such as a thin silicon nitride or amorphous silicon is selectively deposited by limiting deposition time to a period less than incubation time. As a result spacers are formed without having to perform an additional etch act.

Abstract translation: 提供了在栅叠层再氧化之前形成封装间隔物的方法，其防止在再氧化期间形成不期望的金属氧化物。 诸如薄氮化硅或非晶硅的材料通过将沉积时间限制到低于孵育时间的时间来选择性地沉积。 结果形成间隔物，而不必执行另外的蚀刻作用。

公开(公告)号：US20030153142A1

公开(公告)日：2003-08-14

申请号：US10368069

申请日：2003-02-18

Applicant: Micron Technology, Inc.

Inventor： Randhir P.S. Thakur ,  James Pan

IPC: H01L021/8238

CPC classification number: H01L28/84 ,  C23C16/045 ,  C23C16/24 ,  C23C16/56 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02664 ,  H01L27/10852 ,  H01L28/90 ,  H01L28/91 ,  Y10S438/964

Abstract: A polysilicon film is formed with enhanced selectivity by flowing chlorine during the formation of the film. The chlorine acts as an etchant to insulative areas adjacent polysilicon structures on which the film is desired to be formed. Bottom electrodes for capacitors are formed using this process, followed by an anneal to create hemishperical grain (HSG) polysilicon. Multilayer capacitor containers are formed in a non-oxidizing ambient so that no oxide is formed between the layers. The structure formed is planarized to form separate containers made from doped and undoped amorphous silicon layers. Selected ones of undoped layers are seeded in a chlorine containing environment and annealed to form HSG. A dielectric layer and second electrode are formed to complete the cell capacitor.

公开(公告)号：US20030057555A1

公开(公告)日：2003-03-27

申请号：US10277688

申请日：2002-10-22

Applicant: Micron Technology, Inc.

Inventor： Randhir P.S. Thakur

IPC: H01L023/48

CPC classification number: H01L21/76831 ,  H01L21/28525 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76879 ,  H01L2924/0002 ,  Y10S257/915 ,  H01L2924/00

Abstract: A new method and structure for an improved contact using doped silicon is provided. The structures are integrated into several higher level embodiments. The improved contact has low contact resistivity. Improved junctions are thus provided between an IGFET device and subsequent metallization layers. The improvements are obtained through the use of a silicon-germanium (SinullGe) alloy. The alloy can be formed from depositing germanium onto the substrate and subsequently annealing the contact or by selectively depositing the preformed alloy into a contact opening. The above advantages are incorporated with relatively few process steps.

公开(公告)号：US20040238845A1

公开(公告)日：2004-12-02

申请号：US10881630

申请日：2004-06-30

Applicant: Micron Technology. Inc.

Inventor： Yongjun Hu ,  Randhir P.S. Thakur ,  Scott DeBoer

IPC: H01L029/40

CPC classification number: H01L21/28052 ,  H01L21/28061 ,  H01L27/10891 ,  H01L29/4941 ,  Y10S257/914 ,  Y10S257/915

Abstract: Methods and apparatus for forming word line stacks comprise forming a thin nitride layer coupled between a bottom silicon layer and a conductor layer. In a further embodiment, a diffusion barrier layer is coupled between the thin nitride layer and the bottom silicon layer. The thin nitride layer is formed by annealing a silicon oxide film in a nitrogen-containing ambient.

Abstract translation: 用于形成字线堆叠的方法和装置包括形成耦合在底部硅层和导体层之间的薄氮化物层。 在另一个实施例中，扩散阻挡层耦合在薄氮化物层和底部硅层之间。 通过在含氮环境中退火氧化硅膜来形成薄氮化物层。

公开(公告)号：US20030001194A1

公开(公告)日：2003-01-02

申请号：US10232206

申请日：2002-08-29

Applicant: Micron Technology, Inc.

Inventor： Scott Jeffrey DeBoer ,  Husam N. Al-Shareef ,  Randhir P.S. Thakur ,  Dan Gealy

IPC: H01L027/108 ,  H01L029/76 ,  H01L031/119

CPC classification number: H01L21/02326 ,  G11C17/16 ,  H01L21/02183 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/31604 ,  H01L21/31637 ,  H01L23/5252 ,  H01L27/10852 ,  H01L27/10861 ,  H01L27/112 ,  H01L27/11206 ,  H01L28/40 ,  H01L28/65 ,  H01L28/84 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electrode is formed on the tantalum oxynitride film.

公开(公告)号：US20020163056A1

公开(公告)日：2002-11-07

申请号：US10188472

申请日：2002-07-02

Applicant: Micron Technology, Inc.

Inventor： Randhir P.S. Thakur ,  Kevin G. Donohoe ,  Zhiqiang Wu ,  Alan R. Reinberg

IPC: H01L029/00

CPC classification number: H01L21/32 ,  H01L21/0332

Abstract: Mechanical stress is diminished by forming an oxidation mask with silicon nitride having a graded silicon concentration. Grading is accomplished by changing the silicon content in the silicon nitride. The silicon nitride can be graded in a substantially linear or non-linear fashion. In one embodiment, the graded silicon nitride may be formed with one type of non-linear silicon grading, an abrupt junction. In other embodiments, the silicon nitride is formed in a variety of shapes fashioned during or after silicon nitride growth. In one embodiment, the stress is reduced by forming a polysilicon buffer layer between two silicon nitride layers. In another embodiment, stress is reduced by forming the silicon nitride on a pad layer, which in turn is formed on a base layer.

Abstract translation: 通过用具有梯度硅浓度的氮化硅形成氧化掩模来减小机械应力。 通过改变氮化硅中的硅含量来实现分级。 氮化硅可以以基本线性或非线性方式分级。 在一个实施例中，渐变氮化硅可以用一种类型的非线性硅分级，突变结形成。 在其它实施例中，氮化硅形成为在氮化硅生长期间或之后形成的各种形状。 在一个实施例中，通过在两个氮化硅层之间形成多晶硅缓冲层来减小应力。 在另一个实施例中，通过在衬底层上形成氮化硅来降低应力，衬底层又形成在基底层上。