公开(公告)号：US20240429905A1

公开(公告)日：2024-12-26

申请号：US18591581

申请日：2024-02-29

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis ,  Chulkyu Lee

IPC: H03K3/356 ,  H03K19/0185 ,  H03K19/0944

Abstract: A device includes a signal path including a plurality of inverters connected in series, which comprises a first inverter having a first input and a having first output, a second inverter having a second input coupled to the first output of the first inverter and having a second output, and a third inverter having a third input coupled to the second output of the second inverter and having a third output. The device also includes a first feedback path connecting the second output of the second inverter to the first input of the first inverter, the first feedback path including a fourth inverter and a second feedback path connecting the third output of the third inverter to the second input of the second inverter, the second feedback path including a fifth inverter.

公开(公告)号：US20240323062A1

公开(公告)日：2024-09-26

申请号：US18734721

申请日：2024-06-05

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

IPC: H04L25/03 ,  H04L25/49

CPC classification number: H04L25/03057 ,  H04L25/4917

Abstract: Described apparatuses and methods are directed to equalization with pulse-amplitude modulation (PAM) signaling. As bus frequencies have increased, the time for correctly transitioning between voltage levels has decreased, which can lead to errors. Symbol decoding reliability can be improved with equalization, like with decision-feedback equalization (DFE). DFE, however, can be expensive for chip area and power usage. Therefore, instead of applying DFE to all voltage level determination paths in a receiver, DFE can be applied to a subset of such determination paths. With PAM4 signaling, for example, a DFE circuit can be coupled between an output and an input of a middle slicer. In some cases, symbol detection reliability can be maintained even with fewer DFE circuits by compressing a middle eye of the PAM4 signal. The other two eyes thus have additional headroom for expansion. Encoding schemes, impedance terminations, or reference voltage levels can be tailored accordingly.

公开(公告)号：US11775460B2

公开(公告)日：2023-10-03

申请号：US17864023

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G11C5/02 ,  G11C5/06 ,  G11C11/4093 ,  G11C7/10 ,  G11C11/4096 ,  G11C5/04

CPC classification number: G06F13/1689 ,  G06F13/4068 ,  G06F13/42 ,  G06F13/4234 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/1069 ,  G11C11/4093 ,  G11C11/4096

Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.

公开(公告)号：US20230275016A1

公开(公告)日：2023-08-31

申请号：US18312801

申请日：2023-05-05

Applicant: Micron Technology, Inc.

Inventor： David K. Ovard ,  Thomas Hein ,  Timothy M. Hollis ,  Walter L. Moden

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L24/16 ,  H01L23/49822 ,  H01L23/49816 ,  H01L2924/18161 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: Apparatuses may include a device substrate including a microelectronic device and bond pads proximate to an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball positioned and configured to carry a high-bandwidth data signal or a high-frequency clock signal may be located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry a high-bandwidth data signal or a high-frequency clock signal. Each ball positioned and configured to carry a high-bandwidth data signal may be located only diagonally adjacent to any other balls configured to carry a high-bandwidth data signal or a high-frequency clock signal.

公开(公告)号：US20230120654A1

公开(公告)日：2023-04-20

申请号：US18084135

申请日：2022-12-19

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis ,  James S. Rehmeyer ,  Baekkyu Choi ,  Yogesh Sharma ,  Eric J. Stave ,  Brian W. Huber ,  Miles S. Wiscombe

IPC: G11C11/406

Abstract: Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.

公开(公告)号：US11626145B2

公开(公告)日：2023-04-11

申请号：US17360922

申请日：2021-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: H04L25/03 ,  H04B3/32 ,  G11C7/10

Abstract: Embodiments of the disclosure include signal processing methods to reduce crosstalk between signal lines of a channel bus using feed forward equalizers (FFEs) configured smear pulse response energy transmitted on signal lines of the channel to reduce pulse edge rates. The coefficients for the FFE may be based on crosstalk interference characteristics. Smearing or spreading pulse response energy across a longer time period using a FFE increases inter-symbol interference (ISI). To counter increased inter-symbol interference caused by smearing pulse response energy, receivers configured to recover symbol data transmitted on the channel bus may each include respective decision-feedback equalizers (DFEs) that are configured to filter ISI from transmitted symbols based on previous symbol decisions of the channel. The combination of the FFE configured to smear pulse responses and the DFE to filter ISI may improve data eye quality for recovery of transmitted data on a channel bus when crosstalk dominates noise.

公开(公告)号：US20230084286A1

公开(公告)日：2023-03-16

申请号：US17991489

申请日：2022-11-21

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  George E. Pax ,  Yogesh Sharma ,  Gregory A. King ,  Chan H. Yoo ,  Randon K. Richards ,  Timothy M. Hollis

IPC: G11C7/22 ,  G11C16/10 ,  G11C7/10

Abstract: Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.

公开(公告)号：US11606229B2

公开(公告)日：2023-03-14

申请号：US17381987

申请日：2021-07-21

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis ,  Feng Lin

IPC: H04L25/49 ,  H04L27/34 ,  H04L27/04 ,  G06F13/40 ,  G06F1/324 ,  G06F13/16 ,  H04L27/06

Abstract: Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify vertical alignment between data transmitted using multi-level signaling. Such multi-level signaling may be configured to capture transmitted data during a single clock cycle of a memory controller. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

公开(公告)号：US20230075962A1

公开(公告)日：2023-03-09

申请号：US17821604

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Shindeok Kang ,  Timothy M. Hollis

IPC: G11C7/10 ,  H03K7/02

Abstract: This document describes apparatuses and techniques for termination of a pulse amplitude modulation signal of a memory circuit. In various aspects, a memory circuit is implemented with a termination circuit that includes a power rail, a resistor, and a switch to couple the resistor between the power rail and a signal line of a memory interconnect. The power rail may be configured to provide power at a termination voltage that is nominally half of a voltage of another power rail from which a corresponding transmission circuit operates. This may be effective to enable termination of pulse amplitude modulation signals to the termination voltage instead of a higher voltage that corresponds to the power rail of the transmission circuit or a ground-referenced node. By so doing, use of the termination circuit may reduce power consumption and/or improve signal integrity of the memory circuit.

公开(公告)号：US11568913B2

公开(公告)日：2023-01-31

申请号：US17164738

申请日：2021-02-01

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis ,  James S. Rehmeyer ,  Baekkyu Choi ,  Yogesh Sharma ,  Eric J. Stave ,  Brian W. Huber ,  Miles S. Wiscombe

IPC: G11C11/406

Abstract: Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.