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    Computation method and apparatus exploiting weight sparsity
    1.
    发明授权
    Computation method and apparatus exploiting weight sparsity 有权

    公开(公告)号：US11526328B2

    公开(公告)日：2022-12-13

    申请号：US16781868

    申请日：2020-02-04

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Hung-Sheng Chang ,  Han-Wen Hu ,  Hsiang-Pang Li ,  Tzu-Hsien Yang ,  I-Ching Tseng ,  Hsiang-Yun Cheng ,  Chia-Lin Yang

    IPC: G06F7/544 ,  G06N3/04 ,  G11C13/00

    Abstract: A computation method and a computation apparatus exploiting weight sparsity, adapted for a processor to perform multiply-and-accumulate operations on a memory including multiple input and output lines crossing each other. In the method, weights are mapped to the cells of each operation unit (OU) in the memory. The rows of the cells of each OU are compressed by removing at least one row of the cells each mapped with a weight of 0, and an index including values each indicating a distance between every two rows of the cells including at least one cell mapped with a non-zero weight for each OU is encoded. Inputs are inputted to the input lines corresponding to the rows of each OU excluding the rows of the cells with the weight of 0 according to the index and outputs are sensed from the output lines corresponding to the OU to compute a computation result.

    COMPUTATION METHOD AND APPARATUS EXPLOITING WEIGHT SPARSITY
    2.
    发明申请
    COMPUTATION METHOD AND APPARATUS EXPLOITING WEIGHT SPARSITY 有权

    公开(公告)号：US20210240443A1

    公开(公告)日：2021-08-05

    申请号：US16781868

    申请日：2020-02-04

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Hung-Sheng Chang ,  Han-Wen Hu ,  Hsiang-Pang Li ,  Tzu-Hsien Yang ,  I-Ching Tseng ,  Hsiang-Yun Cheng ,  Chia-Lin Yang

    IPC: G06F7/544 ,  G06N3/04 ,  G11C13/00

    Abstract: A computation method and a computation apparatus exploiting weight sparsity, adapted for a processor to perform multiply-and-accumulate operations on a memory including multiple input and output lines crossing each other. In the method, weights are mapped to the cells of each operation unit (OU) in the memory. The rows of the cells of each OU are compressed by removing at least one row of the cells each mapped with a weight of 0, and an index including values each indicating a distance between every two rows of the cells including at least one cell mapped with a non-zero weight for each OU is encoded. Inputs are inputted to the input lines corresponding to the rows of each OU excluding the rows of the cells with the weight of 0 according to the index and outputs are sensed from the output lines corresponding to the OU to compute a computation result.

    MEMORY DEVICE AND ASSOCIATED ERASE METHOD
    4.
    发明申请
    MEMORY DEVICE AND ASSOCIATED ERASE METHOD 有权
    存储器件和相关的擦除方法

    公开(公告)号：US20160300617A1

    公开(公告)日：2016-10-13

    申请号：US14684561

    申请日：2015-04-13

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Ming Chang ,  Hsiang-Pang Li ,  Hung-Sheng Chang ,  Chih-Chang Hsieh ,  Kuo-Pin Chang

    IPC: G11C16/16

    CPC classification number: G11C16/16 ,  G11C16/14 ,  G11C16/18

    Abstract: A memory device and an erase method for the memory device are provided. The memory device includes plural blocks and a controller. The plural blocks include at least one first block and at least one second block. The erase method is controlled by the controller and includes the following steps. A first stage erase operation and a second stage erase operation are sequentially performed on the at least one first block in a first time interval and a second time interval. The first stage erase operation and the second stage erase operation are sequentially performed on the at least one second block in the second time interval and a third time interval.

    Abstract translation: 提供了一种用于存储器件的存储器件和擦除方法。 存储装置包括多个块和控制器。 多个块包括至少一个第一块和至少一个第二块。 擦除方法由控制器控制，包括以下步骤。 在第一时间间隔和第二时间间隔中对至少一个第一块依次执行第一阶段擦除操作和第二阶段擦除操作。 在第二时间间隔和第三时间间隔中，对至少一个第二块依次执行第一级擦除操作和第二级擦除操作。

    Memory device and associated erase method
    5.
    发明授权
    Memory device and associated erase method 有权
    存储器和相关的擦除方法

    公开(公告)号：US09466384B1

    公开(公告)日：2016-10-11

    申请号：US14684561

    申请日：2015-04-13

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Ming Chang ,  Hsiang-Pang Li ,  Hung-Sheng Chang ,  Chih-Chang Hsieh ,  Kuo-Pin Chang

    IPC: G11C11/34 ,  G11C16/16 ,  G11C16/18 ,  G11C16/14

    CPC classification number: G11C16/16 ,  G11C16/14 ,  G11C16/18

    Abstract: A memory device and an erase method for the memory device are provided. The memory device includes plural blocks and a controller. The plural blocks include at least one first block and at least one second block. The erase method is controlled by the controller and includes the following steps. A first stage erase operation and a second stage erase operation are sequentially performed on the at least one first block in a first time interval and a second time interval. The first stage erase operation and the second stage erase operation are sequentially performed on the at least one second block in the second time interval and a third time interval.

    Abstract translation: 提供了一种用于存储器件的存储器件和擦除方法。 存储装置包括多个块和控制器。 多个块包括至少一个第一块和至少一个第二块。 擦除方法由控制器控制，包括以下步骤。 在第一时间间隔和第二时间间隔中对至少一个第一块依次执行第一阶段擦除操作和第二阶段擦除操作。 在第二时间间隔和第三时间间隔中，对至少一个第二块依次执行第一级擦除操作和第二级擦除操作。

    Data storage for artificial intelligence-based applications
    6.
    发明授权
    Data storage for artificial intelligence-based applications 有权

    公开(公告)号：US11914860B2

    公开(公告)日：2024-02-27

    申请号：US15999604

    申请日：2018-08-20

    Applicant: Macronix International Co., Ltd.

    Inventor： Chun-Hung Lai ,  Hung-Sheng Chang

    IPC: G06F3/06 ,  G06N3/063

    CPC classification number: G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G06N3/063

    Abstract: A processor receives, from an input device, input data for processing. Upon determining that the input data corresponds to an artificial intelligence (AI) application, the processor generates an AI command for performing read or write operations for a memory device that is configured to store data for a plurality of applications including the AI application, the AI command characterized by an operational code and including information about one or more components of the AI application corresponding to the input data. The processor sends the AI command and the input data to a storage controller managing the memory device, wherein the read or write operations for the memory device are performed by the storage controller using the operational code and the information included in the AI command. The processor receives, from the storage controller, a result of the read or write operations performed on the memory device.

    DATA MANAGEMENT METHOD AND SYSTEM FOR MEMORY DEVICE
    7.
    发明申请
    DATA MANAGEMENT METHOD AND SYSTEM FOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20190034118A1

    公开(公告)日：2019-01-31

    申请号：US15662348

    申请日：2017-07-28

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Hung-Sheng Chang ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

    IPC: G06F3/06

    Abstract: A data management method for a memory device includes: counting a system time; when at least a part of a block of the memory device is accessed or refreshed or programmed at first time, assigning a block number of the block to point to a maximum remaining retention time; when a first downgrade trigger time reaches, assigning the block number to point from the maximum remaining retention time to a medium remaining retention time; when a second downgrade trigger time reaches, assigning the block number to point from the medium remaining retention time to a minimum remaining retention time; and once the block number points to the minimum remaining retention time, refreshing the block and assigning the block number to point to the maximum remaining retention time.

    MEMORY SYSTEM AND A DATA MANAGING METHOD THEREOF
    9.
    发明申请
    MEMORY SYSTEM AND A DATA MANAGING METHOD THEREOF 有权
    存储器系统及其数据管理方法

    公开(公告)号：US20160154593A1

    公开(公告)日：2016-06-02

    申请号：US14811970

    申请日：2015-07-29

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Hung-Sheng Chang ,  Hsiang-Pang Li ,  Chun-Ta Lin ,  Yuan-Hao Chang ,  Tei-Wei Kuo

    IPC: G06F3/06

    CPC classification number: G06F3/0673 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0641

    Abstract: A memory system is provided. The memory system includes a memory controller and a first memory block. The first memory block is configured to store a first data from a top of the first memory block in a top-down fashion. The first memory block is configured to store a first metadata corresponding to the first data from a bottom of the first memory block in a bottom-up fashion. The first data forms a first data area. The first metadata forms a first metadata area. And a first continuous space is formed between a bottom of the first data area and a top of the first metadata area.

    Abstract translation: 提供了一种存储系统。 存储器系统包括存储器控制器和第一存储器块。 第一存储块被配置为以自顶向下的方式存储来自第一存储器块的顶部的第一数据。 第一存储器块被配置为以自下而上的方式存储来自第一存储器块的底部的与第一数据相对应的第一元数据。 第一数据形成第一数据区。 第一个元数据形成第一个元数据区域。 并且在第一数据区域的底部和第一元数据区域的顶部之间形成第一连续空间。

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