中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

11 records (took 0.026 seconds)

    Method and apparatus for leakage suppression in flash memory in response to external commands
    2.
    发明授权
    Method and apparatus for leakage suppression in flash memory in response to external commands 有权
    响应于外部命令，闪存中泄漏抑制的方法和装置

    公开(公告)号：US09093172B2

    公开(公告)日：2015-07-28

    申请号：US14249270

    申请日：2014-04-09

    Applicant: Macronix International Co., Ltd.

    Inventor： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

    IPC: G11C11/34 ,  G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/14

    CPC classification number: G11C16/3409 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/14

    Abstract: Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.

    Abstract translation: 本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。 在一个实施例中，闪存器件包括包括多个存储单元块的存储器阵列。 该设备还包括用于从存储设备外部的源接收命令的命令接口。 该装置还包括控制器，其包括响应于该命令执行泄漏抑制处理的逻辑。 泄漏抑制处理包括执行软程序操作以增加给定的存储单元块中的一个或多个过擦除存储器单元的阈值电压并建立擦除状态。

    Retention logic for non-volatile memory
    4.
    发明授权
    Retention logic for non-volatile memory 有权
    非易失性存储器的保留逻辑

    公开(公告)号：US09147501B2

    公开(公告)日：2015-09-29

    申请号：US13903574

    申请日：2013-05-28

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chun-Hsiung Hung ,  Nai-Ping Kuo ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Yu-Chen Wang

    IPC: G11C29/00 ,  G11C29/12 ,  G11C16/34

    CPC classification number: G11C16/34 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/349 ,  G11C29/12005 ,  G11C29/50004 ,  G11C29/50016

    Abstract: An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state characterized by a minimum threshold exceeding a selected read bias. A controller includes a stand-by mode, a write mode and a read mode. Retention check logic executes on power-up, or during the stand-by mode, to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells.

    Abstract translation: 集成电路存储器件包括非易失性电荷捕获存储器单元的阵列，其被配置为使用阈值状态将数据值存储在阵列中的存储器单元中，所述阈值状态包括以超过所选择的读偏差的最小阈值为特征的较高阈值状态。 控制器包括待机模式，写入模式和读取模式。 保持检查逻辑在上电或待机模式下执行，以识别在阈值保持检查失败的较高阈值状态下的存储器单元。 此外，提供逻辑以重新编程所识别的存储器单元。

    METHOD AND APPARATUS FOR LEAKAGE SUPPRESSION IN FLASH MEMORY IN RESPONSE TO EXTERNAL COMMANDS
    5.
    发明申请
    METHOD AND APPARATUS FOR LEAKAGE SUPPRESSION IN FLASH MEMORY IN RESPONSE TO EXTERNAL COMMANDS 有权
    FLASH存储器中对外部命令的泄漏抑制方法和装置

    公开(公告)号：US20140219026A1

    公开(公告)日：2014-08-07

    申请号：US14249270

    申请日：2014-04-09

    Applicant: Macronix International Co., Ltd.

    Inventor： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

    IPC: G11C16/34

    CPC classification number: G11C16/3409 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/14

    Abstract: Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.

    Abstract translation: 本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。 在一个实施例中，闪存器件包括包括多个存储单元块的存储器阵列。 该设备还包括用于从存储设备外部的源接收命令的命令接口。 该装置还包括控制器，其包括响应于该命令执行泄漏抑制处理的逻辑。 泄漏抑制处理包括执行软程序操作以增加给定的存储单元块中的一个或多个过擦除存储器单元的阈值电压并建立擦除状态。

    Configurable security memory region
    6.
    发明授权
    Configurable security memory region 有权

    公开(公告)号：US10809925B2

    公开(公告)日：2020-10-20

    申请号：US16259268

    申请日：2019-01-28

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Ken-Hui Chen ,  Kuen-Long Chang ,  Chin-Hung Chang ,  Yu-Chen Wang

    IPC: G06F3/06 ,  G06F12/14

    Abstract: A memory device comprises a memory array with I/O path and security circuitry coupled to the I/O path of the memory array. The memory device comprises control circuitry, responsive to configuration data, to invoke the security circuitry. The memory device comprises a configuration store, storing the configuration data accessible by the control circuitry to specify location and size of a security memory region in the memory array. Responsive to an external command and the configuration data, the control circuitry can be configured to invoke the security circuitry on an operation specified in the external command in response to accesses into the security memory region, or to not invoke the security circuitry in response to accesses to outside the security memory region.

Patent Agency Ranking