公开(公告)号：US20250133719A1

公开(公告)日：2025-04-24

申请号：US18777365

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Christopher K. Morzano ,  Efe Sinan Ege

IPC: H10B12/00

Abstract: A variety of applications can include a memory device having an array of memory cells, with each of the memory cells having a gate-all-around (GAA) transistor arranged as a hexagonal vertical channel transistor coupled to a capacitor. Access lines can be coupled to gates of the GAA transistors and digit lines can be coupled to pillar channels of the GAA transistors. A lattice can be included between the access lines and the digit lines, where the lattice has dielectric regions between and contacting non-dielectric regions. Each non-dielectric region can be positioned on and contacting a digit line and can contain digit contact junctions to the pillar channels of a set of the GAA transistors extending from the non-dielectric region. Additional devices and methods are disclosed.

公开(公告)号：US11380732B2

公开(公告)日：2022-07-05

申请号：US16941885

申请日：2020-07-29

Applicant: Micron Technology, Inc.

Inventor： Lei Wei ,  Pengyuan Zheng ,  Kevin Lee Baker ,  Efe Sinan Ege ,  Adam Thomas Barton ,  Rajasekhar Venigalla

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.

公开(公告)号：US20220037403A1

公开(公告)日：2022-02-03

申请号：US16941885

申请日：2020-07-29

Applicant: Micron Technology, Inc.

Inventor： Lei Wei ,  Pengyuan Zheng ,  Kevin Lee Baker ,  Efe Sinan Ege ,  Adam Thomas Barton ,  Rajasekhar Venigalla

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.

公开(公告)号：US20250133721A1

公开(公告)日：2025-04-24

申请号：US18777695

申请日：2024-07-19

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Efe Sinan Ege ,  Haitao Liu

IPC: H10B12/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A variety of applications can include a memory device having an array of memory cells arranged as hexagonal cells, with each of the memory cells having a gate-all-around (GAA) transistor coupled to a capacitor. An access line can be coupled to gates of a first set of multiple GAA transistors of the memory cells. A digit line can be coupled to a second set of multiple GAA transistors of the memory cells, where the digit line is wrapped on a sidewall of an active area of each GAA transistor of the second set. Additional devices and methods are disclosed.

公开(公告)号：US20250133720A1

公开(公告)日：2025-04-24

申请号：US18777396

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Efe Sinan Ege

IPC: H10B12/00 ,  G11C11/4091 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A variety of applications can include a memory device having an array of memory cells arranged as hexagonal cells, with each of the memory cells having a gate-all-around (GAA) transistor coupled to a capacitor. An access line can be coupled to gates of a first set of multiple GAA transistors of the memory cells. A digit line can be coupled to a second set of multiple GAA transistors of the memory cells, where the digit line is separated from an adjacent digit line by an airgap. Additional devices and methods are disclosed.

公开(公告)号：US11778837B2

公开(公告)日：2023-10-03

申请号：US17846731

申请日：2022-06-22

Applicant: Micron Technology, Inc.

Inventor： Lei Wei ,  Pengyuan Zheng ,  Kevin Lee Baker ,  Efe Sinan Ege ,  Adam Thomas Barton ,  Rajasekhar Venigalla

IPC: H01L27/24 ,  H01L45/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/84 ,  H10N70/063 ,  H10N70/231 ,  H10N70/826 ,  H10N70/841 ,  H10N70/8616

Abstract: A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.

公开(公告)号：US20240224825A1

公开(公告)日：2024-07-04

申请号：US18409413

申请日：2024-01-10

Applicant: Micron Technology, Inc.

Inventor： Rajasekhar Venigalla ,  Patrick M. Flynn ,  Josiah Jebaraj Johnley Muthuraj ,  Efe Sinan Ege ,  Kevin Lee Baker ,  Tao Nguyen ,  Davis Weymann

IPC: H10N70/00 ,  G11C13/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/8616 ,  G11C13/0004 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H10B63/84 ,  H10N70/021 ,  H10N70/231 ,  H10N70/826 ,  H10N70/841 ,  G11C13/004 ,  G11C2013/005 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/52 ,  G11C2213/71 ,  H10N70/8825

Abstract: Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.

公开(公告)号：US11882774B2

公开(公告)日：2024-01-23

申请号：US17468167

申请日：2021-09-07

Applicant: Micron Technology, Inc.

Inventor： Rajasekhar Venigalla ,  Patrick M. Flynn ,  Josiah Jebaraj Johnley Muthuraj ,  Efe Sinan Ege ,  Kevin Lee Baker ,  Tao Nguyen ,  Davis Weymann

IPC: H10N70/00 ,  H01L21/768 ,  H01L23/522 ,  G11C13/00 ,  H01L23/528 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/8616 ,  G11C13/0004 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5226 ,  H10B63/84 ,  H10N70/021 ,  H10N70/231 ,  H10N70/826 ,  H10N70/841 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/005 ,  G11C2013/0078 ,  G11C2213/52 ,  G11C2213/71 ,  H10N70/8825

Abstract: Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.

公开(公告)号：US20220406847A1

公开(公告)日：2022-12-22

申请号：US17846731

申请日：2022-06-22

Applicant: Micron Technology, Inc.

Inventor： Lei Wei ,  Pengyuan Zheng ,  Kevin Lee Baker ,  Efe Sinan Ege ,  Adam Thomas Barton ,  Rajasekhar Venigalla

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.

公开(公告)号：US20220069216A1

公开(公告)日：2022-03-03

申请号：US17468167

申请日：2021-09-07

Applicant: Micron Technology, Inc.

Inventor： Rajasekhar Venigalla ,  Patrick M. Flynn ,  Josiah Jebaraj Johnley Muthuraj ,  Efe Sinan Ege ,  Kevin Lee Baker ,  Tao Nguyen ,  Davis Weymann

IPC: H01L45/00 ,  H01L21/768 ,  H01L23/522 ,  H01L27/24 ,  G11C13/00 ,  H01L23/528

Abstract: Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.