公开(公告)号：US20210218388A1

公开(公告)日：2021-07-15

申请号：US17214262

申请日：2021-03-26

Applicant: Micron Technology, Inc.

Inventor： Guan Wang ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam

IPC: H03K3/017 ,  G06F1/04 ,  G06F1/10 ,  G11C7/22 ,  H04L25/06 ,  G11C29/02 ,  H03K5/156 ,  H04L7/00 ,  H04L25/02

Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock distortion calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

公开(公告)号：US10937505B2

公开(公告)日：2021-03-02

申请号：US16412627

申请日：2019-05-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Xiaojiang Guo ,  Guanglei An ,  Qiang Tang

IPC: G11C16/12 ,  G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34 ,  G11C8/08

Abstract: Methods of operating a memory include determining a target voltage level for an access line voltage, determining a target overdrive voltage level for gating the access line voltage to an access line coupled to a plurality of memory cells, generating a voltage level for the access line voltage in response to its target voltage level and generating a voltage level for gating the access line voltage to the access line in response to the target overdrive voltage level, and applying the access line voltage to the access line while applying the voltage level for gating the access line voltage to a control gate of a string driver connected to the access line. Apparatus include a voltage regulator having variable resistance paths between a voltage signal node and an output node, and between the voltage signal node and an input of a comparator of the voltage regulator.

公开(公告)号：US10727816B2

公开(公告)日：2020-07-28

申请号：US16204841

申请日：2018-11-29

Applicant: Micron Technology, Inc.

Inventor： Guan Wang ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam

IPC: G06F1/10 ,  H03K3/017 ,  H04L25/06 ,  H03K5/156 ,  G11C7/22 ,  G11C29/02 ,  H04L7/00 ,  H04L25/02 ,  G06F1/04

Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

公开(公告)号：US10360956B2

公开(公告)日：2019-07-23

申请号：US15834279

申请日：2017-12-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam ,  Qiang Tang ,  Eric N. Lee

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/06 ,  G11C8/06 ,  G11C8/04 ,  G11C8/18 ,  G11C16/04

Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.

公开(公告)号：US20190180801A1

公开(公告)日：2019-06-13

申请号：US15834279

申请日：2017-12-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam ,  Qiang Tang ,  Eric N. Lee

IPC: G11C7/22 ,  G11C7/06 ,  G11C8/06 ,  G11C8/18 ,  G11C8/04 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1057 ,  G11C7/106 ,  G11C8/04 ,  G11C8/06 ,  G11C8/18 ,  G11C16/0483

Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.

公开(公告)号：US20180330793A1

公开(公告)日：2018-11-15

申请号：US15591700

申请日：2017-05-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Theodore T. Pekny

IPC: G11C16/12 ,  G11C11/56 ,  G11C16/14 ,  G11C16/34 ,  G06F11/10 ,  G11C29/52

Abstract: Methods of operating apparatus include receiving user data for programming to a grouping of memory cells of the apparatus, associating an address of the grouping of memory cells with the user data, determining whether power loss to the apparatus is indicated while programming the user data to the grouping of memory cells, and if power loss to the apparatus is indicated while programming the user data to the grouping of memory cells, programming the address of the grouping of memory cells to a different grouping of memory cells of the apparatus. Methods of operating apparatus further include checking whether power loss to the apparatus during programming of user data to a grouping of memory cells of the apparatus is indicated, and, when power loss is indicated, checking feature settings of the apparatus to determine a location of the apparatus containing an address of the grouping of memory cells, and recovering the address of the grouping of memory cells from the determined location.

公开(公告)号：US10121544B2

公开(公告)日：2018-11-06

申请号：US15692565

申请日：2017-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Ramin Ghodsi ,  Toru Tanzawa

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/34 ,  G11C16/08 ,  G11C11/56 ,  G11C16/32

Abstract: Programming methods include applying a voltage to a selected access line commonly connected to a plurality of memory cells, and, while the voltage applied to the selected access line remains at a program voltage without being discharged, electrically connecting a subset of the plurality of memory cells to one data line so that only one memory cell of the subset of the plurality of memory cells is electrically connected to the one data line at a time.

公开(公告)号：US10037797B2

公开(公告)日：2018-07-31

申请号：US15687710

申请日：2017-08-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Xiaojiang Guo ,  Ramin Ghodsi

IPC: G06F12/00 ,  G11C11/56 ,  G11C16/12 ,  G11C16/04 ,  G11C16/34 ,  G06F3/06 ,  G06F12/02 ,  G11C16/10

CPC classification number: G11C11/5628 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0246 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3404 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5622

Abstract: Methods of operating a memory device include applying a programming pulse to a plurality of memory cells selected for programming having an initial portion having a first voltage level and a subsequent portion having a second voltage level less than the first voltage level, inhibiting a particular memory cell of the plurality of memory cells from programming during the initial portion of the programming pulse while a different memory cell of the plurality of memory cells is enabled for programming, and inhibiting the different memory cell from programming during the subsequent portion of the programming pulse while the particular memory cell is enabled for programming.

公开(公告)号：US09972363B2

公开(公告)日：2018-05-15

申请号：US15444980

申请日：2017-02-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang

IPC: G11C5/14 ,  G06F13/40 ,  H03K19/00 ,  H03K19/0175

CPC classification number: G11C5/14 ,  G06F13/4072 ,  G06F13/4086 ,  H03H11/28 ,  H03K19/0005 ,  H03K19/017545 ,  H03K19/018557

Abstract: Apparatus include a data bus and a signal driver circuit having pluralities of first and second termination devices connected in parallel between a voltage node and an output node. Each of the termination devices is configured to be deactivated in response to control signals having a particular set of logic levels, and to be activated in response to control signals having a set of logic levels other than the particular set of logic levels. Activated second termination devices each exhibit respective resistances greater than a particular resistance of each activated first termination device. Methods include connecting a node of an apparatus to a first voltage node through a reference resistance, connecting the node to a second voltage node through a termination device, and comparing a resulting voltage level to a reference voltage different than half-way between voltage levels of the first and second voltage nodes.

公开(公告)号：US20180076710A1

公开(公告)日：2018-03-15

申请号：US15815037

申请日：2017-11-16

Applicant: Micron Technology, Inc.

Inventor： Xiaojiang Guo ,  Qiang Tang

IPC: H02M3/07 ,  G11C5/14

CPC classification number: G11C5/147 ,  G11C5/145 ,  G11C11/4074 ,  G11C16/30

Abstract: Apparatuses and methods for mixed charge pumps with voltage regulator circuits is disclosed. An example apparatus comprises a first charge pump circuit configured to provide a first voltage, a second charge pump circuit configured to provide a second voltage, a plurality of coupling circuits configured to voltage couple and current couple the first voltage and the second voltage to a common node to provide a regulated voltage, and a feedback circuit configured to regulate the first voltage and the second voltage based on the regulated voltage.