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    SELECTIVE MANAGEMENT OF ERASE OPERATIONS IN MEMORY DEVICES THAT ENABLE SUSPEND COMMANDS
    1.
    发明申请
    SELECTIVE MANAGEMENT OF ERASE OPERATIONS IN MEMORY DEVICES THAT ENABLE SUSPEND COMMANDS 有权

    公开(公告)号：US20230063656A1

    公开(公告)日：2023-03-02

    申请号：US17591510

    申请日：2022-02-02

    Applicant: Micron Technology, Inc.

    Inventor： Chulbum Kim ,  Brian Kwon ,  Erwin E. Yu ,  Kitae Park ,  Taehyun Kim

    IPC: G11C16/14 ,  G11C16/04 ,  G11C16/22 ,  G11C16/32 ,  G06F3/06

    Abstract: A memory device includes a memory array of memory cells and control logic operatively coupled with the memory array. The control logic is to perform operations including: initiating a true erase sub-operation by causing an erase pulse to be applied to one or more sub-blocks of the memory array; tracking, a number of suspend commands received from a processing device during time periods that a memory line of the memory array is caused to ramp towards an erase voltage of the erase pulse; causing, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation; and in response to the number of suspend commands satisfying a threshold criterion, alerting the processing device to terminate sending suspend commands until after completion of the true erase sub-operation.

    SEEDING BIAS CONTROL FOR SUB-BLOCK GROUPS IN A MEMORY DEVICE
    5.
    发明申请
    SEEDING BIAS CONTROL FOR SUB-BLOCK GROUPS IN A MEMORY DEVICE 有权

    公开(公告)号：US20240428862A1

    公开(公告)日：2024-12-26

    申请号：US18748679

    申请日：2024-06-20

    Applicant: Micron Technology, Inc.

    Inventor： Taehyun Kim ,  Brian Kwon ,  Dong Kyo Shim ,  Kwang Ho Kim ,  Erwin E. Yu ,  Fulvio Rori

    IPC: G11C16/10 ,  G11C16/08 ,  G11C16/34

    Abstract: Control logic in a memory device initiates a program operation to program one or more memory cells of a first sub-block of a memory array, the program operation including a seeding phase. During the seeding phase, a first wordline voltage is caused to be applied to a first wordline segment associated with a first portion of the memory array. During the seeding phase, a second wordline voltage is caused to be applied to a second wordline segment associated with a second portion of the memory array, where the first wordline voltage and the second wordline voltage cause a seeding bias voltage to be applied to the first sub-block group and inhibit application of the seeding bias voltage to the second sub-block group.

    ACCESS CIRCUITRY STRUCTURES FOR THREE-DIMENSIONAL MEMORY ARRAY
    8.
    发明公开
    ACCESS CIRCUITRY STRUCTURES FOR THREE-DIMENSIONAL MEMORY ARRAY 审中-公开

    公开(公告)号：US20240088044A1

    公开(公告)日：2024-03-14

    申请号：US17940715

    申请日：2022-09-08

    Applicant: Micron Technology, Inc.

    Inventor： Collin Howder ,  Taehyun Kim

    IPC: H01L23/535 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

    CPC classification number: H01L23/535 ,  H01L23/5283 ,  H01L27/11556 ,  H01L27/11582

    Abstract: Methods, systems, and devices for access circuitry structures for three-dimensional (3D) memory arrays are described. A memory device may include levels of memory cells over a substrate. To support accessing memory cells at respective levels, the memory device may include a conductive pillar extending through the levels of memory cells and coupled with one or more memory cells at respective levels of memory cells. The memory device may include a bit line and a contact that is configured to couple the bit line with the conductive pillar. The conductive pillar may be formed such that it extends into a portion of the contact, and a contact resistance between the conductive pillar and the bit line may be based on the conductive pillar extending into the portion of the contact.

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