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    MULTILAYER SUBSTRATE
    2.
    发明申请
    MULTILAYER SUBSTRATE 有权
    多层基板

    公开(公告)号：US20150053467A1

    公开(公告)日：2015-02-26

    申请号：US14526698

    申请日：2014-10-29

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Shigetoshi Hayashi ,  Tomoya Yokoyama ,  Takako Sato

    IPC: H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K1/11

    CPC classification number: H05K1/112 ,  H01L23/13 ,  H01L23/15 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/15162 ,  H01L2924/1531 ,  H01L2924/19105 ,  H05K1/0271 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/113 ,  H05K1/116 ,  H05K1/165 ,  H05K3/403 ,  H05K3/4629 ,  H05K2201/083 ,  H05K2201/09145

    Abstract: Provided is a multilayer substrate that can prevent generation of cracks caused by stress generated due to a difference between the coefficient of linear expansion of electrode pads and that of a ceramic material. An electrode pad arranged on a layer below an outermost component mounting electrode pad has a larger area than an area of the component mounting electrode pad. Similarly, an electrode pad arranged on a layer below a component mounting electrode pad has a larger area than an area of the component mounting electrode pad, an electrode pad arranged on a layer below a component mounting electrode pad has a larger area than an area of the component mounting electrode pad, and an electrode pad arranged on a layer below a component mounting electrode pad has a larger area than an area of the component mounting electrode pad.

    Abstract translation: 提供一种多层基板，其可以防止由于电极焊盘的线膨胀系数与陶瓷材料的线性膨胀系数之间的差异而产生的应力产生的裂纹。 布置在最外面部件安装电极焊盘下方的层上的电极焊盘的面积大于部件安装电极焊盘的面积。 类似地，布置在部件安装电极焊盘下方的层上的电极焊盘具有比部件安装电极焊盘的面积更大的面积，布置在部件安装电极焊盘下方的电极焊盘的面积大于 部件安装电极焊盘和布置在部件安装电极焊盘下方的层上的电极焊盘的面积大于部件安装电极焊盘的面积。

    Laminated inductor element and manufacturing method thereof
    3.
    发明授权
    Laminated inductor element and manufacturing method thereof 有权
    层叠电感器元件及其制造方法

    公开(公告)号：US08810352B2

    公开(公告)日：2014-08-19

    申请号：US13955505

    申请日：2013-07-31

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Tomoya Yokoyama ,  Takako Sato ,  Akihiro Ieda ,  Shigetoshi Hayashi ,  Hirokazu Yazaki

    IPC: H01F5/00 ,  H01F27/29 ,  H01L23/12 ,  H01F41/04 ,  H01F17/00 ,  H01F3/14

    CPC classification number: H01F27/29 ,  H01F3/14 ,  H01F17/0033 ,  H01F27/292 ,  H01F41/04 ,  H01F41/046 ,  Y10T29/4902

    Abstract: In a laminated inductor element, outer electrodes and terminal electrodes are electrically connected by via holes, internal wiring lines, and end surface electrodes. The via holes on an upper surface side are provided immediately under the outer electrodes and in a non-magnetic ferrite layer. The via holes on a lower surface side are provided immediately above the terminal electrodes and in a non-magnetic ferrite layer. Since outermost layers are defined by the non-magnetic ferrite layers, a parasitic inductance is not increased, even if the outermost layers are provided with the via holes. In this case, the internal wiring lines are not routed on a surface of the element. Therefore, there is no complication of a wiring pattern, and it is possible to prevent an increase in a mounting area of the element.

    Abstract translation: 在层叠电感器元件中，外部电极和端子电极通过通孔，内部布线和端面电极电连接。 上表面侧的通孔设置在外部电极的正下方和非磁性铁氧体层的下方。 下表面侧的通孔设置在端子电极的正上方和非磁性铁氧体层。 由于最外层由非磁性铁氧体层限定，即使最外层设置有通孔，寄生电感也不会增加。 在这种情况下，内部布线不会在元件的表面上布线。 因此，不存在布线图案的复杂化，可以防止元件的安装面积的增大。

    Multilayer substrate
    5.
    发明授权
    Multilayer substrate 有权
    多层基板

    公开(公告)号：US09204545B2

    公开(公告)日：2015-12-01

    申请号：US14526698

    申请日：2014-10-29

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Shigetoshi Hayashi ,  Tomoya Yokoyama ,  Takako Sato

    IPC: H05K1/11 ,  H05K1/03 ,  H01L23/15 ,  H01L23/498 ,  H05K1/02 ,  H05K1/09 ,  H01L23/13

    CPC classification number: H05K1/112 ,  H01L23/13 ,  H01L23/15 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/15162 ,  H01L2924/1531 ,  H01L2924/19105 ,  H05K1/0271 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/113 ,  H05K1/116 ,  H05K1/165 ,  H05K3/403 ,  H05K3/4629 ,  H05K2201/083 ,  H05K2201/09145

    Abstract: Provided is a multilayer substrate that can prevent generation of cracks caused by stress generated due to a difference between the coefficient of linear expansion of electrode pads and that of a ceramic material. An electrode pad arranged on a layer below an outermost component mounting electrode pad has a larger area than an area of the component mounting electrode pad. Similarly, an electrode pad arranged on a layer below a component mounting electrode pad has a larger area than an area of the component mounting electrode pad, an electrode pad arranged on a layer below a component mounting electrode pad has a larger area than an area of the component mounting electrode pad, and an electrode pad arranged on a layer below a component mounting electrode pad has a larger area than an area of the component mounting electrode pad.

    Abstract translation: 提供一种多层基板，其可以防止由于电极焊盘的线膨胀系数与陶瓷材料的线性膨胀系数之间的差异而产生的应力产生的裂纹。 布置在最外面部件安装电极焊盘下方的层上的电极焊盘的面积大于部件安装电极焊盘的面积。 类似地，布置在部件安装电极焊盘下方的层上的电极焊盘具有比部件安装电极焊盘的面积更大的面积，布置在部件安装电极焊盘下方的电极焊盘的面积大于 部件安装电极焊盘和布置在部件安装电极焊盘下方的层上的电极焊盘的面积大于部件安装电极焊盘的面积。

    Piezoelectric actuator and drive method therefor
    6.
    发明授权
    Piezoelectric actuator and drive method therefor 有权

    公开(公告)号：US11730060B2

    公开(公告)日：2023-08-15

    申请号：US16941705

    申请日：2020-07-29

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Yoshiyuki Yamakawa ,  Seishiro Goto ,  Shinichiro Kawada ,  Shigetoshi Hayashi ,  Akio Fujita ,  Yusuke Nakamura

    IPC: H10N30/853 ,  H10N30/50 ,  H10N30/87

    CPC classification number: H10N30/8536 ,  H10N30/50 ,  H10N30/872

    Abstract: A piezoelectric actuator that includes a multilayer body, a low-potential outer electrode, and a high-potential outer electrode. The multilayer body includes multiple alternately stacked piezoelectric ceramic layers and planar electrodes. The planar electrodes include low-potential planar electrodes electrically connected to the low-potential outer electrode and high-potential planar electrodes electrically connected to the high-potential outer electrode. The planar electrode positioned most outwardly on the side of a first main surface of the multilayer body is a low-potential planar electrode. The inner surface of this low-potential planar electrode contacts the − side of polarization in an active region, and the outer surface of this low-potential planar electrode is exposed on an outside of the multilayer body. On the side of a second main surface of the multilayer body, a high-potential planar electrode is not exposed on the outside of the multilayer body.

    Laminated-type inductance device
    7.
    发明授权
    Laminated-type inductance device 有权

    公开(公告)号：US09601253B2

    公开(公告)日：2017-03-21

    申请号：US14672774

    申请日：2015-03-30

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Tomoya Yokoyama ,  Shigetoshi Hayashi

    IPC: H01F17/04 ,  H01F5/00 ,  H01F27/28 ,  H01F27/24 ,  H01F17/00 ,  H01F3/14

    CPC classification number: H01F17/0013 ,  H01F3/14 ,  H01F17/04

    Abstract: Provided is a laminated-type inductance device capable of reducing the number of layers for sandwiching a non-magnetic body layer and enhancing direct-current superposition characteristics without intentionally providing a space. In a conductive pattern, portions of the outer circumferential section thereof adjacent to end surface electrodes are respectively recessed toward the inside of the pattern when viewed from above. In other words, line widths are narrower at the above portions. Further, non-magnetic paste is formed between the end surface electrode and the outer circumferential section of the conductive pattern at each of the portions where the line width is narrower. By applying the non-negative paste in a space between the conductive pattern and the end surface electrode, the portion where the non-magnetic paste is applied has the same function as in a case where the non-magnetic ferrite layer is inserted therein.

    LAMINATED-TYPE INDUCTANCE DEVICE
    8.
    发明申请
    LAMINATED-TYPE INDUCTANCE DEVICE 有权
    层压型电感器件

    公开(公告)号：US20150206643A1

    公开(公告)日：2015-07-23

    申请号：US14672774

    申请日：2015-03-30

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Tomoya Yokoyama ,  Shigetoshi Hayashi

    IPC: H01F17/00

    CPC classification number: H01F17/0013 ,  H01F3/14 ,  H01F17/04

    Abstract: Provided is a laminated-type inductance device capable of reducing the number of layers for sandwiching a non-magnetic body layer and enhancing direct-current superposition characteristics without intentionally providing a space. In a conductive pattern, portions of the outer circumferential section thereof adjacent to end surface electrodes are respectively recessed toward the inside of the pattern when viewed from above. In other words, line widths are narrower at the above portions. Further, non-magnetic paste is formed between the end surface electrode and the outer circumferential section of the conductive pattern at each of the portions where the line width is narrower. By applying the non-negative paste in a space between the conductive pattern and the end surface electrode, the portion where the non-magnetic paste is applied has the same function as in a case where the non-magnetic ferrite layer is inserted therein.

    Abstract translation: 提供一种层叠型电感器件，其能够减少用于夹持非磁性体层的层数，并且增强直流叠加特性，而无需有意提供空间。 在导电图案中，当从上方观察时，与端面电极相邻的外周部分的部分分别凹入图案的内部。 换句话说，线宽在上述部分较窄。 此外，在线宽较窄的各部分，在导电图案的端面电极与外周部之间形成非磁性浆料。 通过将非负性糊剂施加在导电图案和端面电极之间的空间中，施加非磁性浆料的部分具有与非磁性铁氧体层插入其中的功能相同的功能。

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