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公开(公告)号：US20180324377A1
公开(公告)日：2018-11-08
申请号：US16034226
申请日：2018-07-12
Applicant: OmniVision Technologies, Inc.
Inventor： Fan Zhu , Yu-Shen Yang , Yingkan Lin , Zejian Wang , Liping Deng
Abstract: An example method for fast ramp start-up during analog to digital conversion (ADC) includes opening a feedback bypass switch coupled to an amplifier to initiate an ADC operation, providing an injection current pulse to an inverting input of the amplifier, where the non-inverting input is coupled to a feedback bypass switch, integrating a first reference current coupled to the inverting input of the amplifier, where the integrating of the first reference current occurs due to the opening of the feedback bypass switch, and providing a reference voltage in response to the injection current pulse, the integrating of the first reference current, and a reference voltage coupled to a non-inverting input of the amplifier, where a level of the reference voltage is increased at least at initiation of the ADC operation in response to the injection current pulse.
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公开(公告)号：US09876979B1
公开(公告)日：2018-01-23
申请号：US15371009
申请日：2016-12-06
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Chun-Hsiang Chang , Yu-Shen Yang , Yingkan Lin , Liping Deng
CPC classification number: H04N5/378 , G05F1/575 , H01L27/14643 , H03B5/1271 , H03B5/366 , H03B2201/0275 , H04N5/374 , H04N5/953
Abstract: An example current generator may include a low dropout regulator (LDO) coupled to receive a reference voltage and provide a reference current in response, where the LDO adjusts a current level of the current reference in response to a calibration signal. A current controlled oscillator coupled to receive a reference current copy from the LDO and generate an oscillating signal in response, where a period of the oscillating signal is based at least in part on a level of the reference current copy. A pulse generator coupled to provide an adjustable pulse signal. A counter coupled to determine a number of periods of the oscillating signal occurring during a duration of the pulse signal, and provide a control signal indicative of such, and a digital calibration circuit coupled to receive the control signal and provide the calibration signal to the LDO in response.
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公开(公告)号：US09848152B1
公开(公告)日：2017-12-19
申请号：US15277859
申请日：2016-09-27
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Yingkan Lin , Yu-Shen Yang , Liping Deng
CPC classification number: H04N5/378 , H03M1/0639 , H03M1/56 , H04N5/365
Abstract: Apparatuses and methods for reducing vertical fixed pattern noise in imaging systems are disclosed herein. An example apparatus may include an analog dithering circuit coupled to randomly add an offset voltage to a first reference voltage in response to a random binary signal during an analog to digital conversion operation, and a ramp generator circuit coupled to receive the first reference voltage, and provide a second reference voltage in response, wherein the randomly added offset voltage to the first reference is also present in the second reference voltage.
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公开(公告)号：US11128307B2
公开(公告)日：2021-09-21
申请号：US16175586
申请日：2018-10-30
Applicant: OmniVision Technologies, Inc.
Inventor： Rui Wang , Yu-Shen Yang , Shan Chen , Min Qu
Abstract: An analog to digital conversion (ADC) circuit includes a ramp circuit coupled to output a ramp signal, and the ramp signal is offset from a starting voltage by an offset voltage. The ramp signal ramps towards the starting voltage. A counter circuit is coupled to the ramp circuit to start counting after the ramp signal returns to the starting voltage, and a comparator is coupled to the counter circuit and a bitline to compare the ramp signal to a pixel signal voltage on the bitline. In response to the ramp signal equaling the pixel signal voltage, the comparator stops the counter.
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公开(公告)号：US20210021769A1
公开(公告)日：2021-01-21
申请号：US16516067
申请日：2019-07-18
Applicant: OmniVision Technologies, Inc.
Inventor： Zhe Gao , Ling Fu , Yu-Shen Yang , Tiejun Dai
Abstract: A switch driver circuit includes a first transistor coupled between a voltage supply and a first output node. A second transistor is coupled between the first output node and a first discharge node. A first slope control circuit is coupled to the first discharge node to discharge the first discharge node at a first slope. A third transistor is coupled between the voltage supply and a second output node. A fourth transistor is coupled between the second output node and a second discharge node. A second slope control circuit coupled to the second discharge node to discharge the second discharge node at a second slope. The first and second slopes are mismatched.
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Patent Agency Ranking
公开(公告)号：US11716547B2
公开(公告)日：2023-08-01
申请号：US17530316
申请日：2021-11-18
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Zhe Gao , Ling Fu , Yu-Shen Yang , Tiejun Dai
Abstract: A switch driver circuit includes a plurality of pullup transistors. The plurality of pullup transistors includes a first pullup transistor coupled between a voltage supply and a first output node. A plurality of pulldown transistors includes a first pulldown transistor coupled between the first output node and a ground node. A slope control circuit is coupled to the ground node. A plurality of global connection switches includes a first global connection switch coupled between the first output node and the slope control circuit.
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公开(公告)号：US20210329185A1
公开(公告)日：2021-10-21
申请号：US16854765
申请日：2020-04-21
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Lihang Fan , Min Qu , Yu-Shen Yang , Charles Qingle Wu
Abstract: A readout circuit for use in an image sensor includes a plurality of comparators. Each one of the plurality of comparators is coupled to receive a ramp signal and a respective analog image data signal from a respective one of a plurality of column bit lines to generate a respective comparator output. Each one of a plurality of arithmetic logic units (ALUs) is coupled to receive phase-aligned Gray code (GC) outputs generated by a GC generator. Each one of the plurality of ALUs is further coupled to a respective one of the plurality of comparators to receive the respective comparator output. Each one of the plurality of ALUs is coupled to latch the phase-aligned GC outputs in response to the respective comparator output to generate a respective digital image data signal.
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8.发明授权公开(公告)号：US10326955B1
公开(公告)日：2019-06-18
申请号：US15872709
申请日：2018-01-16
Applicant: OmniVision Technologies, Inc.
Inventor： Yingkan Lin , Charles Wu , Yu-Shen Yang
IPC: H04N5/378 , H04N5/369 , H04N5/3745 , H04N5/376
Abstract: A readout circuit for use with an image sensor includes a comparator coupled to compare a ramp signal from a ramp generator with an output signal from a pixel of a pixel array. A counter is coupled to the comparator to count until the comparator detects that a ramp signal value has reached an output signal value. The counter includes K cascade-coupled dynamic flip-flop circuits to generate the K least significant bits (LSBs) of the N-bit output of the counter. The counter also includes N-K cascade-coupled static flip-flop circuits to generate the N-K most significant bits (MSBs) of the N-bit output of the counter. A latch is coupled to the counter to store a count value generated by the counter after the ramp signal value has reached the output signal value.
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公开(公告)号：US10110837B2
公开(公告)日：2018-10-23
申请号：US15446711
申请日：2017-03-01
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Yingkan Lin , Tiejun Dai , Cheng-Pin Lin , Yu-Shen Yang
Abstract: Methods and apparatuses for data transmission in an image sensor are disclosed herein. An example data transmission circuit may include a plurality of transmission banks coupled in series with a first one of the plurality of transmission banks coupled to function logic, where each of the plurality of transmission banks are coupled to provide image data to a subsequent transmission bank in a direction toward the function logic in response to a clock signal, a plurality of delays coupled in series, wherein each of the plurality of delays is associated with and coupled to a respective transmission bank of the plurality of transmission banks, and wherein the clock signal is received by each of the plurality of transmission banks after being delayed by a respective number of delays of the plurality of delays in relation to the function logic.
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公开(公告)号：US11722801B1
公开(公告)日：2023-08-08
申请号：US17659042
申请日：2022-04-13
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Hiroaki Ebihara , Zhenfu Tian , Tao Sun , Liang Zuo , Yu-Shen Yang , Satoshi Sakurai , Rui Wang
IPC: H04N25/75 , H04N25/772
CPC classification number: H04N25/75 , H04N25/772
Abstract: A ramp buffer circuit includes an input device having an input coupled to receive a ramp signal. A bias current source is coupled to an output of the input device. The input device and the bias current source are coupled between a power line and ground. An assist current source is coupled between the output of the input device and ground. The assist current source is configured to conduct an assist current from the output of the input device to ground only during a ramp event generated in the ramp signal.
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