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公开(公告)号：US10558393B2
公开(公告)日：2020-02-11
申请号：US15789903
申请日：2017-10-20
Applicant: QUALCOMM Incorporated
Inventor： Hyunsuk Shin , David Teb , Hung Vuong
Abstract: A system is proposed to enable a hardware based host controller to perform operations related to Host-aware Performance booster (HPB). The host controller may retrieve a command packet from a host memory targeting a logical address of a storage location of the storage device, may retrieve a physical address of the storage device mapped to the logical address from the address map, and may send the command packet to the storage device. The sent command packet may have the physical address incorporated therein.
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公开(公告)号：US10360987B2
公开(公告)日：2019-07-23
申请号：US16175745
申请日：2018-10-30
Applicant: QUALCOMM Incorporated
Inventor： Hyunsuk Shin , Robert Hardacker , Hung Vuong
Abstract: Systems and method for a host-driven data refresh of a Flash memory include registers provided in the Flash memory for storing various settings related to refresh operations, such as, when to start/stop refreshing, target partitions in the memory, target start/end address ranges for refreshing, refresh algorithms, refresh rate requirements, etc. A host can control the various settings for start/stop refreshing, target partitions in the memory, target start/end address ranges for refreshing, refresh algorithms, through the corresponding registers; and the Flash memory can control various values related to refresh rate requirements through corresponding registers. In this manner, a standard platform or interface is provided within the Flash memory for refresh operations thereof.
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公开(公告)号：US09401226B1
公开(公告)日：2016-07-26
申请号：US14853860
申请日：2015-09-14
Applicant: QUALCOMM Incorporated
Inventor： Hyunsuk Shin , Jung Pill Kim , Sungryul Kim
CPC classification number: G11C29/76 , G06F12/0238 , G06F2212/7207 , G06F2212/7209 , G11C7/20 , G11C11/1653 , G11C29/44 , G11C29/789 , G11C29/808 , G11C29/82 , G11C29/84
Abstract: A device includes a redundant region of a magnetoresistive random access memory (MRAM) array that includes first memory cells. The device includes a data region of the MRAM array that includes second memory cells. The device includes a fail address region of the MRAM array, a first row of the fail address region including validity data, wherein the validity data includes multiple validity indicators, a last row indicator, or both.
Abstract translation: 一种器件包括包含第一存储器单元的磁阻随机存取存储器（MRAM）阵列的冗余区域。 该装置包括包括第二存储器单元的MRAM阵列的数据区域。 该装置包括MRAM阵列的故障地址区域，包括有效性数据的故障地址区域的第一行，其中有效性数据包括多个有效性指示符，最后一行指示符或两者。
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4.发明授权公开(公告)号：US09653183B1
公开(公告)日：2017-05-16
申请号：US15254068
申请日：2016-09-01
Applicant: QUALCOMM Incorporated
Inventor： Hyunsuk Shin , Sungryul Kim , Jung Pill Kim
CPC classification number: G11C29/18 , G11C8/12 , G11C11/165 , G11C11/1677 , G11C29/1201 , G11C29/26 , G11C29/44 , G11C29/4401
Abstract: Shared built-in self-analysis of memory systems employing a memory array tile architecture is provided. To selectively control which memory tile among a plurality of memory tiles is accessed for a built-in self-analysis (BISA) operation, a shared BISA address issued from a shared BISA circuit includes a memory tile address. Each memory tile includes a unique fixed memory tile address that is compared to the received memory tile address of a received BISA address. If the memory tile address in the received BISA address matches the fixed memory tile address of a memory tile, the memory tile is activated to use the memory address in the BISA address to access addressed memory bit cells for analysis. Thus, if the memory system is redesigned to include additional memory tiles for increased capacity, the memory tile address size in the BISA address can be updated for addressing added memory tiles.
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公开(公告)号：US09633706B1
公开(公告)日：2017-04-25
申请号：US15289495
申请日：2016-10-10
Applicant: QUALCOMM Incorporated
Inventor： Sungryul Kim , Jung Pill Kim , Hyunsuk Shin
CPC classification number: G11C11/1657 , G11C8/08 , G11C8/10 , G11C8/18 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/1697
Abstract: A voltage self-boosting circuit for generating a boosted voltage for driving a word line write in a memory array for a memory write operation is provided. A voltage generation circuit(s) is configured to generate a read voltage for a memory read operation and a write voltage for a memory write operation based on a predefined supply voltage. For the memory write operation, a delay circuit delays the delay circuit enable signal by a predetermined delay to generate the output voltage control signal. Accordingly, the voltage generation circuit(s) generates boosted voltage that drives the write voltage to a selected word line(s). For the memory read operation, the voltage generation circuit(s) does not generate the boosted voltage and thus drives the read voltage to the selected word line(s). Hence, it is possible to reduce power consumption and timing delay during the memory read operation or the memory write operation.
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Patent Agency Ranking
公开(公告)号：US09552318B2
公开(公告)日：2017-01-24
申请号：US14295653
申请日：2014-06-04
Applicant: QUALCOMM Incorporated
Inventor： Hyunsuk Shin , Henry Laurel Sanchez , Hung Quoc Vuong , Amit Gil
CPC classification number: G06F13/4022 , G06F13/4068 , G06F13/4234 , G11C16/14 , G11C16/20 , G11C16/34
Abstract: Removable memory card type detection systems and methods are disclosed. In one aspect, a removable memory card is inserted into a receptacle of a host. The host determines a type of removable memory card based upon either electrical or physical properties of the removable memory card. In this manner, if the host detects that the removable memory card possesses certain electrical or physical properties associated with a microSD card, the host determines that the removable memory card is a microSD type card. If the host detects that the removable memory card possesses certain electrical or physical properties associated with a UFS card, the host determines that the removable memory card is a UFS type card. By determining the card type based on detection of certain electrical or physical properties, aspects disclosed herein are able to distinguish between UFS and microSD cards without requiring an additional pin or card initialization time.
Abstract translation: 公开了可移动存储卡型检测系统和方法。 在一个方面，将可移动存储卡插入到主机的插座中。 主机基于可移动存储卡的电气或物理属性来确定可移动存储卡的类型。 以这种方式，如果主机检测到可移动存储卡具有与microSD卡相关联的某些电气或物理属性，则主机确定可移动存储卡是microSD型卡。 如果主机检测到可移动存储卡具有与UFS卡相关联的某些电气或物理属性，则主机确定可移动存储卡是UFS型卡。 通过基于某些电气或物理特性的检测来确定卡类型，本文公开的方面能够区分UFS和microSD卡，而不需要额外的引脚或卡初始化时间。
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公开(公告)号：US09274888B2
公开(公告)日：2016-03-01
申请号：US14081645
申请日：2013-11-15
Applicant: QUALCOMM Incorporated
Inventor： Dexter Tamio Chun , Jung Pill Kim , Hyunsuk Shin , Jungwon Suh
CPC classification number: G06F11/1072 , G06F11/1048 , G06F11/14 , G11C29/765
Abstract: A system for replacing a page stored in system memory when reading the page incurs a multiple-bit error. Upon reading a page in system memory for which a multiple-bit error is detected, backup data in flash memory is loaded into a redundant page in the system memory, and a re-mapper is configured so that future accesses to the page are redirected to the redundant page.
Abstract translation: 当读取页面时，用于替换存储在系统存储器中的页面的系统产生多位错误。 在读取检测到多位错误的系统存储器中的页面时，闪存中的备份数据被加载到系统存储器中的冗余页面中，并且配置重新映射器，以便将来对页面的访问被重定向到 冗余页面。
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公开(公告)号：US11221774B2
公开(公告)日：2022-01-11
申请号：US17011720
申请日：2020-09-03
Applicant: QUALCOMM Incorporated
Inventor： Hyunsuk Shin , Todd Christopher Reynolds , Hung Vuong
IPC: G06F3/06 , G11C5/14 , G06F1/3234 , G11C16/30 , G06F13/16
Abstract: Systems and method are directed to Universal Flash Storage (UFS) memory system configured to support deep power-down modes wherein the UFS memory system is not required to be responsive to commands received from a host device coupled to the UFS memory system. Correspondingly, in the deep power-down modes, a link or interface between the UFS memory system and the host device may also be powered down. The UFS memory system may enter the deep power-down modes based on a command received from the host device or a hardware reset assertion, and exit the deep power-down modes based on a hardware reset de-assertion or power cycling. While in deep power-down modes, the power consumption of the UFS memory device is substantially lower than the power consumption of the UFS memory device in conventional power modes.
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公开(公告)号：US10725706B1
公开(公告)日：2020-07-28
申请号：US16255477
申请日：2019-01-23
Applicant: QUALCOMM Incorporated
Inventor： Madhu Yashwanth Boenapalli , Hyunsuk Shin , Surendra Paravada , Sai Praneeth Sreeram , Venu Madhav Mokkapati
IPC: G06F3/06
Abstract: A method of scheduling universal flash storage (UFS) operations using a refresh handover mechanism is described. The method includes receiving, during refresh of a UFS device, a request for an input/output (I/O) operation. The method also includes handing over between a first type of refresh operation and a second type of refresh operation in response to the request for the I/O operation.
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公开(公告)号：US10199115B2
公开(公告)日：2019-02-05
申请号：US15615827
申请日：2017-06-06
Applicant: QUALCOMM Incorporated
Inventor： Hyunsuk Shin , Robert Hardacker , Hung Vuong
Abstract: Systems and method for a host-driven data refresh of a Flash memory include registers provided in the Flash memory for storing various settings related to refresh operations, such as, when to start/stop refreshing, target partitions in the memory, target start/end address ranges for refreshing, refresh algorithms, refresh rate requirements, etc. A host can control the various settings for start/stop refreshing, target partitions in the memory, target start/end address ranges for refreshing, refresh algorithms, through the corresponding registers; and the Flash memory can control various values related to refresh rate requirements through corresponding registers. In this manner, a standard platform or interface is provided within the Flash memory for refresh operations thereof.
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