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    Clock and Data Recovery Having Shared Clock Generator
    1.
    发明申请
    Clock and Data Recovery Having Shared Clock Generator 审中-公开

    公开(公告)号：US20190007189A1

    公开(公告)日：2019-01-03

    申请号：US16032616

    申请日：2018-07-11

    Applicant: Rambus Inc.

    Inventor： Masum HOSSAIN ,  Brian Leibowitz ,  Jihong Ren

    IPC: H04L7/00 ,  H03L7/23 ,  H04L7/033 ,  H04L27/00 ,  H04L27/32 ,  H03L7/197

    Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

    Methods and circuits for asymmetric distribution of channel equalization between devices
    2.
    发明授权
    Methods and circuits for asymmetric distribution of channel equalization between devices 有权

    公开(公告)号：US10135647B2

    公开(公告)日：2018-11-20

    申请号：US15878149

    申请日：2018-01-23

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

    IPC: H04L25/03

    Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

    METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES
    3.
    发明申请
    METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES 有权
    用于设备之间的通道均衡化的不对称分配的方法和电路

    公开(公告)号：US20170054577A1

    公开(公告)日：2017-02-23

    申请号：US15233557

    申请日：2016-08-10

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

    IPC: H04L25/03

    CPC classification number: H04L25/03343 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03433 ,  H04L2025/03617

    Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

    Abstract translation: 收发器架构支持在高性能集成电路（IC）和使用较不复杂的发送器和接收器的一个或多个相对低性能的IC之间延伸的信号通道上的高速通信。 该架构通过在车道的较高性能侧实例化相对复杂的发送和接收均衡电路来补偿通过双向通道通信的IC之间的性能不对称性。 基于在高性能IC的接收机处的信号响应，可以自适应地更新高性能IC中的发送和接收均衡滤波器系数。

    EDGE BASED PARTIAL RESPONSE EQUALIZATION
    4.
    发明申请
    EDGE BASED PARTIAL RESPONSE EQUALIZATION 审中-公开
    基于边缘部分响应均衡

    公开(公告)号：US20160373277A1

    公开(公告)日：2016-12-22

    申请号：US15178493

    申请日：2016-06-09

    Applicant: Rambus Inc.

    Inventor： Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Ruwan Ratnayake

    IPC: H04L25/03

    CPC classification number: H04L25/03057 ,  G06F13/38 ,  H04L25/03019 ,  H04L25/0307 ,  H04L2025/03369 ,  H04L2025/03617

    Abstract: A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value.

    Abstract translation: 公开了一种方法。 该方法包括对数据信号的预期边沿时间具有电压值的数据信号进行采样。 产生第一个α值，并根据电压值生成第二个alpha值。 数据信号被调整为第一个α值以导出第一个调整的信号。 数据信号通过第二α值进行调整，以得到第二调整信号。 第一调整后的信号被采样以输出第一数据值，而第二调整信号被采样以输出第二数据值。 作为先前接收的数据值的函数，在第一数据值和第二数据值之间进行选择，以确定接收到的数据值。

    Edge based partial response equalization
    6.
    发明授权
    Edge based partial response equalization 有权
    基于边缘的部分响应均衡

    公开(公告)号：US08811553B2

    公开(公告)日：2014-08-19

    申请号：US13932561

    申请日：2013-07-01

    Applicant: Rambus Inc.

    Inventor： Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Ruwan Ratnayake

    IPC: H03H7/30 ,  H04B1/10 ,  H04L27/06 ,  H04L7/00

    CPC classification number: H04L25/03057 ,  G06F13/38 ,  H04L25/03019 ,  H04L25/0307 ,  H04L2025/03369 ,  H04L2025/03617

    Abstract: A device implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit that sets the tap weights that are used for adjustment of a received data signal. The tap weight adapter circuit sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal may be generated as a function of the signals of the edge samplers and prior data values determined by the equalizer.

    Abstract translation: 设备实现基于边缘的部分响应判决反馈均衡的数据接收。 在一个示例性实施例中，该设备实现一个抽头权重适配器电路，其设置用于调整接收到的数据信号的抽头权重。 抽头重量适配器电路基于先前确定的数据值设置抽头权重，并使用一组边缘采样器从接收数据信号的边缘分析输入。 边缘分析可以包括通过由抽头权重适配器电路确定的抽头权重来调整采样的数据信号。 时钟发生电路产生边沿时钟信号，以控制由边缘采样器组执行的边缘采样。 可以根据边缘采样器的信号和由均衡器确定的先前数据值来生成边沿时钟信号。

    METHODS AND CIRCUITS FOR REDUCING CLOCK JITTER
    7.
    发明申请
    METHODS AND CIRCUITS FOR REDUCING CLOCK JITTER 有权
    减少时钟抖动的方法和电路

    公开(公告)号：US20140152357A1

    公开(公告)日：2014-06-05

    申请号：US13878351

    申请日：2011-10-03

    Applicant: RAMBUS INC.

    Inventor： Jared Zerbe ,  Teva Stone ,  Jihong Ren

    IPC: H03L7/00

    CPC classification number: H04L7/02 ,  H03K5/1252 ,  H03L7/00

    Abstract: A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

    Abstract translation: 通信系统包括时钟转发路径中的连续时间线性均衡器。 可以调整均衡器以使时钟抖动最小化，包括在使能时钟信号之后与前几个时钟沿相关联的抖动。 降低早期的抖动可以降低功耗和电路复杂度，否则需要快速打开系统。

    HIGH-ACCURACY DETECTION IN COLLABORATIVE TRACKING SYSTEMS
    8.
    发明申请
    HIGH-ACCURACY DETECTION IN COLLABORATIVE TRACKING SYSTEMS 有权
    协同跟踪系统的高精度检测

    公开(公告)号：US20130162460A1

    公开(公告)日：2013-06-27

    申请号：US13726822

    申请日：2012-12-26

    Applicant: Rambus Inc.

    Inventor： Farshid Aryanfar ,  Jihong Ren

    IPC: G01S5/02

    CPC classification number: G01S5/0294 ,  A63F2300/204 ,  G01S13/767

    Abstract: An electronic device for wirelessly tracking the position of a second electronic device is disclosed. The electronic device includes transceiver circuitry and processing circuitry. The transceiver circuitry includes a beacon generator to generate a beacon at a particular frequency and direction. An antenna array transmits the beacon, and receives at least one modulated reflected beacon from the second electronic device. The transceiver circuitry also includes a discriminator to discriminate between received modulated reflected beacons and received reflected interfering beacons. The processing circuitry couples to the transceiver circuitry and tracks the position of the second device based on the modulated reflected beacons.

    Abstract translation: 公开了一种用于无线跟踪第二电子设备的位置的电子设备。 电子设备包括收发器电路和处理电路。 收发器电路包括用于在特定频率和方向上产生信标的信标发生器。 天线阵列发送信标，并从第二电子设备接收至少一个经调制的反射信标。 收发器电路还包括鉴别器以区分接收到的被调制反射信标和接收到的反射干涉信标。 处理电路耦合到收发器电路并且基于经调制的反射信标来跟踪第二设备的位置。

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