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公开(公告)号：US11646724B2
公开(公告)日：2023-05-09
申请号：US17668584
申请日：2022-02-10
Applicant: Rambus Inc.
Inventor： Charles Walter Boecker , Roxanne Vu , Eric Douglas Groen
CPC classification number: H03K5/13 , H03K3/356104 , H03K5/135 , H03K2005/00019
Abstract: Disclosed is a system where indicators of the relative phase differences between combinations of clocks in a multi-phase clock system are developed and/or measured. These indicators convey information regarding which phase difference between a given pair of the clocks is greater than (or less than) the phase difference between another pair of the clocks. This information is used to sort/rank/order phase differences between the various combinations of pairs of clocks according to their phase differences. This ranking is used to select the pair of clocks to be adjusted.
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公开(公告)号：US20170005785A1
公开(公告)日：2017-01-05
申请号：US15176864
申请日：2016-06-08
Applicant: Rambus Inc.
Inventor： Marko Aleksic , Simon Li , Roxanne Vu
CPC classification number: H04L7/033 , H03L7/081 , H04L7/0004 , H04L7/0079 , H04L7/0337 , H04L25/03
Abstract: A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.
Abstract translation: 具有时钟相位校准的接收器。 第一采样电路基于输入信号，由第一时钟信号控制的第一采样电路的采样相位产生第一数字数据。 第二采样电路基于输入信号产生第二数字数据，由第二时钟信号控制的第二采样电路的采样相位。 接收机内的电路校准不同阶段的时钟。 在第一校准阶段期间，在选择第一数字数据以产生输出数据的同时调整第二时钟信号的相位。 在第二校准阶段期间，在为输出数据路径选择第一数字数据的同时调整第一时钟信号的相位。
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公开(公告)号：US11283435B2
公开(公告)日：2022-03-22
申请号：US16721116
申请日：2019-12-19
Applicant: Rambus Inc.
Inventor： Charles Walter Boecker , Roxanne Vu , Eric Douglas Groen
Abstract: Disclosed is a system where indicators of the relative phase differences between combinations of clocks in a multi-phase clock system are developed and/or measured. These indicators convey information regarding which phase difference between a given pair of the clocks is greater than (or less than) the phase difference between another pair of the clocks. This information is used to sort/rank/order phase differences between the various combinations of pairs of clocks according to their phase differences. This ranking is used to select the pair of clocks to be adjusted.
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公开(公告)号：US10310999B2
公开(公告)日：2019-06-04
申请号：US15702987
申请日：2017-09-13
Applicant: Rambus Inc.
Inventor： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
IPC: G06F13/364 , G06F13/42 , G06F1/10 , G06F13/16 , H04L7/00 , G11C7/10 , G06F12/02 , G06F3/06 , G06F13/40 , H04L7/033
Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.
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公开(公告)号：US09405678B2
公开(公告)日：2016-08-02
申请号：US14859991
申请日：2015-09-21
Applicant: Rambus Inc.
Inventor： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
CPC classification number: G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.
Abstract translation: 集成电路装置包括发射机电路，其可操作以通过第一导线将定时信号发送到DRAM。 DRAM接收具有平衡数量的逻辑零到一转换和一到零转换的第一信号，并且在定时信号的上升沿采样第一信号以产生相应的采样值。 该装置还包括一个接收器电路，用于从与第一线分开的多个线上的DRAM接收相应的采样值。 在第一模式中，发射机电路重复地将定时信号的增量偏移版本发送到DRAM，直到从DRAM接收到的采样值从逻辑0变为逻辑0，反之亦然; 并且在第二模式中，它根据基于采样值产生的写定时偏移，将多条线上的写数据发送到DRAM。
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Patent Agency Ranking
6.发明授权Memory controller with circuitry to set memory device-specific reference voltages 有权存储器控制器，具有设置存储器特定参考电压的电路公开(公告)号：US08948212B2
公开(公告)日：2015-02-03
申请号：US14154068
申请日：2014-01-13
Applicant: Rambus Inc.
Inventor： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
CPC classification number: G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.
Abstract translation: 集成电路装置包括发射机电路，其可操作以通过第一导线将定时信号发送到DRAM。 DRAM接收具有平衡数量的逻辑零到一转换和一到零转换的第一信号，并且在定时信号的上升沿采样第一信号以产生相应的采样值。 该装置还包括一个接收器电路，用于从与第一线分开的多个线上的DRAM接收相应的采样值。 在第一模式中，发射机电路重复地将定时信号的增量偏移版本发送到DRAM，直到从DRAM接收到的采样值从逻辑0变为逻辑0，反之亦然; 并且在第二模式中，它根据基于采样值产生的写定时偏移，将多条线上的写数据发送到DRAM。
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公开(公告)号：US20180013544A1
公开(公告)日：2018-01-11
申请号：US15659394
申请日：2017-07-25
Applicant: Rambus Inc.
Inventor： Marko Aleksic , Simon Li , Roxanne Vu
CPC classification number: H04L7/033 , H03L7/081 , H04L7/0004 , H04L7/0079 , H04L7/0337 , H04L25/03
Abstract: A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.
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公开(公告)号：US20170031854A1
公开(公告)日：2017-02-02
申请号：US15222987
申请日：2016-07-29
Applicant: Rambus Inc.
Inventor： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
IPC: G06F13/364 , G06F13/42 , G06F13/40 , G06F3/06
CPC classification number: G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.
Abstract translation: 集成电路装置包括发射机电路，其可操作以通过第一导线将定时信号发送到DRAM。 DRAM接收具有平衡数量的逻辑零到一转换和一到零转换的第一信号，并且在定时信号的上升沿采样第一信号以产生相应的采样值。 该装置还包括一个接收器电路，用于从与第一线分开的多个线上的DRAM接收相应的采样值。 在第一模式中，发射机电路重复地将定时信号的增量偏移版本发送到DRAM，直到从DRAM接收到的采样值从逻辑0变为逻辑0，反之亦然; 并且在第二模式中，它根据基于采样值产生的写定时偏移，将多条线上的写数据发送到DRAM。
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公开(公告)号：US10658987B2
公开(公告)日：2020-05-19
申请号：US16206864
申请日：2018-11-30
Applicant: Rambus Inc.
Inventor： Richelle L. Smith , Roxanne Vu , Carl W. Werner
IPC: H03F1/56 , H03F3/45 , H03K19/195 , H01L27/12 , H03F1/30 , H01L27/092
Abstract: The embodiments herein describe technologies of an amplifier circuit that is designed for wideband communication with superconductive components in cryogenic applications, including Josephson Junction integrated circuits, operating in a cryogenic temperature domain (e.g., 4K). The amplifier circuit operates in a temperature domain (e.g., 77K) that is higher than the cryogenic temperature domain of the superconductive components.
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公开(公告)号：US20190190463A1
公开(公告)日：2019-06-20
申请号：US16206864
申请日：2018-11-30
Applicant: Rambus Inc.
Inventor： Richelle L. Smith , Roxanne Vu , Carl W. Werner
IPC: H03F1/56 , H03F3/45 , H03K19/195 , H01L27/12 , H03F1/30
CPC classification number: H03F1/56 , H01L27/0928 , H01L27/1203 , H03F1/301 , H03F3/45228 , H03F2200/129 , H03F2200/222 , H03F2200/294 , H03F2200/462 , H03F2203/45288 , H03F2203/45528 , H03K19/195
Abstract: The embodiments herein describe technologies of an amplifier circuit that is designed for wideband communication with superconductive components in cryogenic applications, including Josephson Junction integrated circuits, operating in a cryogenic temperature domain (e.g., 4K). The amplifier circuit operates in a temperature domain (e.g., 77K) that is higher than the cryogenic temperature domain of the superconductive components.
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