公开(公告)号：US20160005727A1

公开(公告)日：2016-01-07

申请号：US14851696

申请日：2015-09-11

Applicant: Renesas Electronics Corporation

Inventor： Shintaro YAMAMACHI ,  Kenta OGAWA

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/48

CPC classification number: H01L25/18 ,  H01L21/561 ,  H01L23/12 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2924/00

Abstract: This invention can reduce heat that is generated in a first semiconductor chip and transfers to a second semiconductor chip through through-silicon vias. The first semiconductor chip has the first through-silicon vias. Each of the first through-silicon vias is arranged on any of grid points arranged in m rows and n columns (m>n). The first semiconductor chip also has a first circuit formation area. A first circuit is formed in the first circuit formation area. The first circuit performs signal processing while communicating with the second semiconductor chip. In plan view, the first circuit formation area does not overlap with a through-silicon via area that is defined by coupling the outermost grid points arranged in m rows and n columns. In plan view, some of connection terminals are located between the first circuit formation area and the through-silicon via area.

Abstract translation: 本发明可以减少在第一半导体芯片中产生的热量并通过硅通孔转移到第二半导体芯片。 第一个半导体芯片具有第一个穿硅通孔。 第一贯穿硅通孔中的每一个布置在以m行和n列（m> n）排列的网格点中的任一个上。 第一半导体芯片也具有第一电路形成区域。 第一电路形成在第一电路形成区域中。 第一电路在与第二半导体芯片通信的同时执行信号处理。 在平面图中，第一电路形成区域不与通过将以m行和n列布置的最外边界点相耦合而定义的通硅通孔区域重叠。 在平面图中，一些连接端子位于第一电路形成区域和穿硅通孔区域之间。

公开(公告)号：US20130130442A1

公开(公告)日：2013-05-23

申请号：US13741910

申请日：2013-01-15

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka NAKASHIBA ,  Kenta OGAWA

IPC: H01L21/56

CPC classification number: H01L23/5227 ,  H01L21/56 ,  H01L23/48 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49575 ,  H01L23/544 ,  H01L23/645 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0657 ,  H01L2223/6655 ,  H01L2224/04042 ,  H01L2224/29 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83855 ,  H01L2224/85 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/0635 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.

Abstract translation: 第一半导体芯片和第二半导体芯片在第一多层互连层和第二多层互连层彼此相对的方向上彼此重叠。 当在平面图中看到时，第一电感器和第二电感器重叠。 第一半导体芯片和第二半导体芯片具有不相对的非对置区域。 第一多层互连层在非对置区域中具有第一外部连接端子，并且第二多层互连层在非对置区域中具有第二外部连接端子。

公开(公告)号：US20130127033A1

公开(公告)日：2013-05-23

申请号：US13741879

申请日：2013-01-15

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka NAKASHIBA ,  Kenta OGAWA

IPC: H01L23/495

CPC classification number: H01L23/5227 ,  H01L21/56 ,  H01L23/48 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49575 ,  H01L23/544 ,  H01L23/645 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0657 ,  H01L2223/6655 ,  H01L2224/04042 ,  H01L2224/29 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83855 ,  H01L2224/85 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/0635 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.

Abstract translation: 第一半导体芯片和第二半导体芯片在第一多层互连层和第二多层互连层彼此相对的方向上彼此重叠。 当在平面图中看到时，第一电感器和第二电感器重叠。 第一半导体芯片和第二半导体芯片具有不相对的非对置区域。 第一多层互连层在非对置区域中具有第一外部连接端子，并且第二多层互连层在非对置区域中具有第二外部连接端子。