公开(公告)号：US20240178144A1

公开(公告)日：2024-05-30

申请号：US18521994

申请日：2023-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Hyeonjin SHIN ,  Sangwon KIM ,  Changhyun KIM ,  Baekwon PARK ,  Kyung-Eun BYUN

IPC: H01L23/532

CPC classification number: H01L23/53276 ,  H01L23/53295

Abstract: An interconnect structure may include a first dielectric layer including a trench, a first conductive layer in the trench and including a plurality of first graphene layers stacked in a direction from an inner surface of the trench toward a center of the trench, a second dielectric layer on the first dielectric layer and including a through hole extending to the trench, and a second conductive layer in the through hole.

公开(公告)号：US20230163023A1

公开(公告)日：2023-05-25

申请号：US18054970

申请日：2022-11-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungjoo AN ,  Jungsoo YOON ,  Soyoung LEE ,  Keunwook SHIN

IPC: H01L21/764 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L21/764 ,  H01L21/7682 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method of fabricating a semiconductor device including a two-dimensional material layer defining an air-gap, and the semiconductor device therefrom are provided. The method of fabricating a semiconductor device, includes forming a structure on a substrate, wherein the structure has an opening; loading the substrate into a process chamber; forming at least one two-dimensional material layer on an upper surface of the structure so as to overlie the opening and form an air-gap, wherein an upper portion of the air-gap is defined by the at least one two-dimensional material layer; and unloading the substrate from the process chamber.

公开(公告)号：US20230112883A1

公开(公告)日：2023-04-13

申请号：US17690376

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Keunwook SHIN ,  Junyoung KWON ,  Minseok YOO ,  Changseok LEE

IPC: H01L29/76 ,  H01L29/16 ,  H01L29/24 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Provided are a two-dimensional material structure, a semiconductor device including the two-dimensional material structure, and a method of manufacturing the semiconductor device. The two-dimensional material structure may include a first insulator including a first dielectric material; a second insulator on the first insulator and including a second dielectric material; a first two-dimensional material film on an exposed surface of the first insulator; and a second two-dimensional material film provided on an exposed surface of the second insulator. The first and second two-dimensional material films may include a two-dimensional material having a two-dimensional layered structure, and the second two-dimensional material film may include more layers of the two-dimensional material than the first two-dimensional material film.

公开(公告)号：US20230079680A1

公开(公告)日：2023-03-16

申请号：US17829679

申请日：2022-06-01

Applicant: Samsung Electronics Co., Ltd. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Keunwook SHIN ,  Kibum KIM ,  Kyung-Eun BYUN ,  Hyeonjin SHIN ,  Minhyun LEE ,  Changseok LEE

IPC: C01B32/186 ,  C01B32/188 ,  H01L29/41 ,  H01L29/40

Abstract: Provided are a wiring including a graphene layer and a method of manufacturing the wiring. The method may include growing a graphene layer on a substrate and doping the graphene layer with a metal. The graphene layer may be grown using a plasma of a hydrocarbon at a temperature of about 200° C. to about 600° C. by plasma enhanced chemical vapor deposition (PECVD).

公开(公告)号：US20220316052A1

公开(公告)日：2022-10-06

申请号：US17711147

申请日：2022-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwon KIM ,  Kyung-Eun BYUN ,  Yeonchoo CHO ,  Keunwook SHIN ,  Eunkyu LEE ,  Changseok LEE ,  Hyunjae SONG ,  Hyeonjin SHIN ,  Jungsoo YOON ,  Soyoung LEE ,  Hyunseok LIM

IPC: C23C16/26 ,  H01L29/45 ,  H01L21/285 ,  C23C16/511 ,  C23C16/505 ,  C23C16/02

Abstract: Provided are nanocrystalline graphene and a method of forming the same. The nanocrystalline graphene may include a plurality of grains formed by stacking a plurality of graphene sheets and has a grain density of about 500 ea/μm2 or higher and a root-mean-square (RMS) roughness in a range of about 0.1 or more to about 1.0 or less. When the nanocrystalline graphene has a grain density and a RMS roughness with these ranges, nanocrystalline graphene capable of covering the entirety of a large area on a substrate as a thin layer may be provided.

公开(公告)号：US20220173221A1

公开(公告)日：2022-06-02

申请号：US17398363

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjin SHIN ,  Sangwon KIM ,  Kyung-Eun BYUN ,  Hyunjae SONG ,  Keunwook SHIN ,  Eunkyu LEE ,  Changseok LEE ,  Yeonchoo CHO ,  Taejin CHOI

IPC: H01L29/45 ,  H01L27/108 ,  H01L29/15 ,  H01L29/40

Abstract: An interconnect structure for reducing a contact resistance, an electronic device including the same, and a method of manufacturing the interconnect structure are provided. The interconnect structure includes a semiconductor layer including a first region having a doping concentration greater than a doping concentration of a peripheral region of the semiconductor layer, a metal layer facing the semiconductor layer, a graphene layer between the semiconductor layer and the metal layer, and a conductive metal oxide layer between the graphene layer and the semiconductor and covering the first region.

公开(公告)号：US20210296465A1

公开(公告)日：2021-09-23

申请号：US17173604

申请日：2021-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehwan MOON ,  Keunwook SHIN ,  Jinseong HEO

IPC: H01L29/51 ,  H01L29/08 ,  H01L29/06

Abstract: Disclosed are a semiconductor device and a capacitor which have relatively less leakage current. The semiconductor device includes a semiconductor layer, an oxide layer disposed on the semiconductor layer, and a metal layer disposed on the oxide layer, and a hydrogen concentration in the oxide layer is about 0.7 at % or more.

公开(公告)号：US20250107208A1

公开(公告)日：2025-03-27

申请号：US18976637

申请日：2024-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun KIM ,  Seunggeol NAM ,  Keunwook SHIN ,  Dohyun LEE

IPC: H01L29/45 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes a first source/drain structure including a first semiconductor region and a first electrode in electrical contact with the first semiconductor region; a second source/drain structure including a second semiconductor region and a second electrode in electrical contact with the second semiconductor region; a channel between the first semiconductor region and the second semiconductor region; and a gate structure including a gate insulating film covering the channel and a gate electrode covering the gate insulating film. The first source/drain structure further includes a silicide film between the first semiconductor region and the first electrode and a conductive barrier between the silicide film and the first electrode. The conductive barrier includes a conductive two-dimensional material.

公开(公告)号：US20240021676A1

公开(公告)日：2024-01-18

申请号：US18331463

申请日：2023-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun KIM ,  Minsu SEOL ,  Junyoung KWON ,  Keunwook SHIN ,  Minseok YOO

IPC: H01L29/18 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417 ,  H01L29/06 ,  H01L29/775 ,  H10B10/00 ,  H10B43/27

CPC classification number: H01L29/18 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/41733 ,  H01L29/0673 ,  H01L29/775 ,  H10B10/125 ,  H10B43/27

Abstract: A semiconductor device includes a channel including a two-dimensional (2D) semiconductor material, a source electrode and a drain electrode electrically connected to opposite sides of the channel, respectively, a transition metal oxide layer on the channel and including a transition metal oxide, a dielectric layer on the transition metal oxide layer and including a high-k material, and a gate electrode on the dielectric layer.

公开(公告)号：US20230123234A1

公开(公告)日：2023-04-20

申请号：US17703201

申请日：2022-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Kyung-Eun BYUN ,  Sangsoo LEE ,  Changhyun KIM ,  Changseok LEE

IPC: H01L29/786 ,  H01L29/16 ,  H01L27/11597 ,  H01L27/11582

Abstract: Provided is a thin film structure including a substrate, a metal layer on the substrate and spaced apart from the substrate, and a two-dimensional material layer between the substrate and the metal layer. The two-dimensional material layer may be configured to limit and/or block an electron transfer between the substrate and the metal layer. A resistivity of a metal layer on the two-dimensional material layer may be lowered by the two-dimensional material layer.