公开(公告)号：US10797030B2

公开(公告)日：2020-10-06

申请号：US15867686

申请日：2018-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangnam Jeong ,  IlJoon Kim ,  SunWon Kang

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/522 ,  H01L23/48 ,  H01L23/538 ,  H01L23/50 ,  H01L23/498

Abstract: Disclosed is a semiconductor package including a semiconductor chip, a first outer capacitor on the semiconductor chip including a first electrode and a second electrode, a second outer capacitor on the semiconductor chip including a first electrode pattern and a second electrode pattern, and a conductive pattern on the semiconductor chip and electrically connected to the first electrode of the first outer capacitor and the first electrode pattern of the second outer capacitor. The second electrode of the first outer capacitor is insulated from the second electrode pattern of the second outer capacitor.

公开(公告)号：US10985138B2

公开(公告)日：2021-04-20

申请号：US15855205

申请日：2017-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SunWon Kang ,  Won-young Kim

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L25/10 ,  H01L23/31

Abstract: A semiconductor package includes a first interconnect substrate on a first redistribution substrate and having a first opening penetrating the first interconnect substrate. A first semiconductor chip is on the first redistribution substrate and the first opening of the first interconnect substrate. A second redistribution substrate is on the first interconnect substrate and the first semiconductor chip. A second interconnect substrate is on the second redistribution substrate and has a second opening penetrating the second interconnect substrate. A second semiconductor chip is on the second redistribution substrate and in the second opening of the second interconnect substrate.

公开(公告)号：US11769746B2

公开(公告)日：2023-09-26

申请号：US17189405

申请日：2021-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ae-Nee Jang ,  KyungSeon Hwang ,  SunWon Kang

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/48

CPC classification number: H01L24/14 ,  H01L21/563 ,  H01L23/481 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/73 ,  H01L24/03 ,  H01L24/06 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/0557 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/10125 ,  H01L2224/1147 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13564 ,  H01L2224/13582 ,  H01L2224/14104 ,  H01L2224/14515 ,  H01L2224/14517 ,  H01L2224/26145 ,  H01L2224/73104 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/11849 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/01074 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2224/131 ,  H01L2924/014

Abstract: A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.

公开(公告)号：US10943881B2

公开(公告)日：2021-03-09

申请号：US16244661

申请日：2019-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ae-nee Jang ,  KyungSeon Hwang ,  SunWon Kang

IPC: H01L23/488 ,  H01L23/00 ,  H01L21/56 ,  H01L23/48

Abstract: A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.

公开(公告)号：US10211176B2

公开(公告)日：2019-02-19

申请号：US15375196

申请日：2016-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ae-nee Jang ,  KyungSeon Hwang ,  SunWon Kang

IPC: H01L27/146 ,  H01L23/00 ,  H01L21/56 ,  H01L23/48

Abstract: A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.

公开(公告)号：US11018121B2

公开(公告)日：2021-05-25

申请号：US16438430

申请日：2019-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangnam Jeong ,  IlJoon Kim ,  SunWon Kang

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/522 ,  H01L23/48 ,  H01L23/538 ,  H01L23/50 ,  H01L23/498

Abstract: Disclosed is a semiconductor package including a semiconductor chip, a first outer capacitor on the semiconductor chip including a first electrode and a second electrode, a second outer capacitor on the semiconductor chip including a first electrode pattern and a second electrode pattern, and a conductive pattern on the semiconductor chip and electrically connected to the first electrode of the first outer capacitor and the first electrode pattern of the second outer capacitor. The second electrode of the first outer capacitor is insulated from the second electrode pattern of the second outer capacitor.

公开(公告)号：US10720408B2

公开(公告)日：2020-07-21

申请号：US16684569

申请日：2019-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungsoo Kim ,  SunWon Kang

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/498 ,  H01L23/50 ,  H01L25/10

Abstract: A semiconductor module, comprising: a module substrate with an electric connection element; at least one semiconductor package provided on the module substrate, the at least one semiconductor package including a plurality of semiconductor chips; and a connection region electrically connecting the semiconductor package to the module substrate, wherein the connection region comprises: a first region electrically connected between data signal terminals of a first chip of the semiconductor chips of the semiconductor package and the module substrate; a second region electrically connected between data signal terminals of a second chip of the semiconductor chips of the semiconductor package and the module substrate; and a third region electrically connected between command/address signal terminals of both the first and second chips of the semiconductor package and the module substrate, wherein the first region is closer to the electric connection element of the module substrate, compared with the third region.