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    PROGRAMMING TECHNIQUES IN A MEMORY DEVICE TO REDUCE A HYBRID SLC RATIO
    1.
    发明公开
    PROGRAMMING TECHNIQUES IN A MEMORY DEVICE TO REDUCE A HYBRID SLC RATIO 审中-公开

    公开(公告)号：US20240242764A1

    公开(公告)日：2024-07-18

    申请号：US18222735

    申请日：2023-07-17

    Applicant: SanDisk Technologies LLC

    Inventor： Huiwen Xu ,  Deepanshu Dutta ,  Jia Li ,  Bo Lei ,  Ken Oowada

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08

    CPC classification number: G11C16/102 ,  G11C16/0433 ,  G11C16/08

    Abstract: The memory device includes a plurality of hybrid memory blocks that can operate in either a single bit per memory cell mode or a multiple bits per memory cell mode. The memory blocks each include a plurality of memory cells, which are arranged in a plurality of word lines. Control circuitry is configured to program a selected word line to an SLC format. The control circuitry is further configured to determine which zone within the selected hybrid memory block the selected word line is located in and set an SLC programming voltage to a level based on the determination of the zone of the selected word line. The control circuitry is further configured to apply a programming pulse at the SLC programming voltage to the selected word line to program the memory cells of the selected word line.

    NON-VOLATILE MEMORY WITH SWITCHABLE ERASE METHODS
    4.
    发明申请
    NON-VOLATILE MEMORY WITH SWITCHABLE ERASE METHODS 有权

    公开(公告)号：US20220101926A1

    公开(公告)日：2022-03-31

    申请号：US17034086

    申请日：2020-09-28

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Ken Oowada ,  Huai-Yuan Tseng

    IPC: G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/08 ,  G11C16/34

    Abstract: To improve the erase process, multiple methods of erasing are utilized. A first method of erasing is relied on at the beginning of life of the memory system. A second method is increasingly relied on as the memory system is used and undergoes many program/erase cycles. In one example, the first method of erase includes applying an erase enable voltage separately to different subsets of the word lines while word lines not receiving the erase enable voltage receive an erase inhibit voltage. In one example, the second method of erase includes applying an erase enable voltage concurrently to all subsets of the word lines.

    CONCURRENT PROGRAMMING OF MULTIPLE CELLS FOR NON-VOLATILE MEMORY DEVICES
    5.
    发明申请
    CONCURRENT PROGRAMMING OF MULTIPLE CELLS FOR NON-VOLATILE MEMORY DEVICES 有权

    公开(公告)号：US20210358553A1

    公开(公告)日：2021-11-18

    申请号：US17360572

    申请日：2021-06-28

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Gerrit Jan Hemink ,  Ken Oowada ,  Toru Miwa

    IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C8/18 ,  G11C8/12

    Abstract: Technology is disclosed herein for concurrently programming the same data pattern in multiple sets of non-volatile memory cells. Voltage are applied to bit lines in accordance with a data pattern. A select voltage is applied to drain select gates of multiple sets of NAND strings. The system concurrently applies a program pulse to control gates of a different set of selected memory cells in each respective set of the multiple sets of the NAND strings while the select voltage is applied to the drain select gates of the multiple sets of the NAND strings and the voltages are applied to the plurality of bit lines to concurrently program the data pattern into each set of the selected memory cells.

    Programming memory cells with concurrent redundant storage of data for power loss protection
    10.
    发明授权
    Programming memory cells with concurrent redundant storage of data for power loss protection 有权

    公开(公告)号：US11625172B2

    公开(公告)日：2023-04-11

    申请号：US17349306

    申请日：2021-06-16

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Toru Miwa ,  Ken Oowada ,  Gerrit Jan Hemink

    IPC: G06F3/06

    Abstract: Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. One or more initial pages of data are programmed into both a primary block and a first backup block in a first program pass. A power loss then occurs which can corrupt the data or otherwise prevent reading of the one or more initial pages of data from the primary block. The one or more initial pages of data are read from the first backup block and used to perform a second program pass in which one or more additional pages of data are programmed into the primary block. Single bit per cell data can be stored in a second backup block to decode the one or more initial pages of data as read from the first backup block.

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