公开(公告)号：US10984877B1

公开(公告)日：2021-04-20

申请号：US16717233

申请日：2019-12-17

Applicant: SanDisk Technologies LLC

Inventor： Jongyeon Kim ,  Hiroki Yabe ,  Kou Tei ,  Chia-Kai Chou ,  Ohwon Kwon

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/26 ,  G11C11/56 ,  G11C16/10 ,  G11C16/24

Abstract: An apparatus and method for a multi-state verify of a memory array are provided. A sense circuit of a memory device is connected to a bit line of the memory array. The sense circuit includes a first voltage clamp, a second voltage clamp, and a program data latch disposed on the bit line. The first and second voltage clamps are biased to first and second voltages, respectively, where the first voltage is lower than the second voltage. When a high bias is applied to the program data latch, the program data latch is in an OFF state, and the first voltage clamp limits the bias on the bit line to the first voltage. When a low bias is applied to the program data latch, the program data latch is in an ON state, and the second voltage clamp limits the bias on the bit line to the second voltage.

公开(公告)号：US20240215240A1

公开(公告)日：2024-06-27

申请号：US18358584

申请日：2023-07-25

Applicant: SanDisk Technologies LLC

Inventor： Ohwon Kwon ,  Yuki Mizutani ,  Arka Ganguly ,  Kou Tei ,  Yonggang Wu

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: Technology is disclosed herein for a memory device having a narrow gap between planes and a method of shrinking the gap between planes. A first and second adjacent planes each has a word line (WL) hookup region at mid-plane. A dummy array region resides between the two planes. The dummy array region may contain a stack of alternating layers of a first insulating material and a second insulating material. There is a first electrical isolation structure between the dummy array region and a stack in the first plane. There is a second electrical isolation structure between the dummy array region and a stack in a second plane. The electrical isolation structures may be formed in narrow trenches. The combination of the dummy array region and the two electrical isolation structures results in a very short gap between the adjacent planes.

公开(公告)号：US11978516B2

公开(公告)日：2024-05-07

申请号：US17718124

申请日：2022-04-11

Applicant: SanDisk Technologies LLC

Inventor： Yanjie Wang ,  Ohwon Kwon ,  Kou Tei ,  Tai-Yuan Tseng ,  Yasue Yamamoto ,  Yonggang Wu ,  Guirong Liang

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  H01L23/00 ,  H01L25/065

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24 ,  G11C16/30 ,  G11C16/3459 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/08148 ,  H01L2224/16225 ,  H01L2224/48149 ,  H01L2224/48229 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06562

Abstract: A memory system having a dynamic supply voltage to sense amplifiers. The supply voltage has a higher magnitude when charging inhibited bit lines during a program operation and a lower magnitude when verifying/sensing memory cells. Reducing the magnitude of the supply voltage saves power and/or current. However, if the lower magnitude were used when the inhibited bit lines are charged during the program operations, some of the memory cells that should be inhibited from programming might experience at least some programming. Using the higher magnitude supply voltage during bit line charging of the program operation assures that the inhibited bit lines are charged to a sufficient voltage to keep drain side select gates of NAND strings off so that the NAND channel will boost properly to inhibit programming of such memory cells.

公开(公告)号：US12057175B2

公开(公告)日：2024-08-06

申请号：US17715647

申请日：2022-04-07

Applicant: SanDisk Technologies LLC

Inventor： Chin-Yi Chen ,  Muhammad Masuduzzaman ,  Kou Tei ,  Deepanshu Dutta ,  Hiroyuki Mizukoshi ,  Jiahui Yuan ,  Xiang Yang

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3459 ,  G11C11/5621 ,  G11C11/5671

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in memory holes and grouped into a plurality of tiers. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states to store one bit as single-level cells and a plurality of bits as multi-level cells. The apparatus also includes a control means coupled to the word lines and the memory holes and configured to select a predetermined strobe quantity of the plurality of tiers of the memory cells separately for the memory cells operating as the single-level cells and the memory cells operating as the multi-level cells. The control means is also configured to trigger sensing of the predetermined strobe quantity of the plurality of tiers of the memory cells during a verify operation.

公开(公告)号：US11881266B2

公开(公告)日：2024-01-23

申请号：US17667169

申请日：2022-02-08

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Kou Tei ,  Ohwon Kwon

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings. The memory cells are configured to retain a threshold voltage. The rows include full circle rows and semi-circle rows in which the memory holes are partially cut by a slit half etch. The memory holes of the semi-circle rows are coupled semi-circle bit lines and the memory holes of the full circle rows are coupled to full circle bit lines. A control means is configured to erase the memory cells in an erase operation. During the erase operation, the control means creates a capacitive coupling between each of the semi-circle bit lines and at least one neighboring one of the full circle bit lines to increase a semi-circle erase voltage applied to each of the semi-circle bit lines.

公开(公告)号：US20230253053A1

公开(公告)日：2023-08-10

申请号：US17667169

申请日：2022-02-08

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Kou Tei ,  Ohwon Kwon

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/26 ,  G11C16/24

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/24 ,  H01L27/11556

Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings. The memory cells are configured to retain a threshold voltage. The rows include full circle rows and semi-circle rows in which the memory holes are partially cut by a slit half etch. The memory holes of the semi-circle rows are coupled semi-circle bit lines and the memory holes of the full circle rows are coupled to full circle bit lines. A control means is configured to erase the memory cells in an erase operation. During the erase operation, the control means creates a capacitive coupling between each of the semi-circle bit lines and at least one neighboring one of the full circle bit lines to increase a semi-circle erase voltage applied to each of the semi-circle bit lines.

公开(公告)号：US11222694B1

公开(公告)日：2022-01-11

申请号：US16985837

申请日：2020-08-05

Applicant: SanDisk Technologies LLC

Inventor： Sirisha Bhamidipati ,  Arka Ganguly ,  Ohwon Kwon ,  Chia-Kai Chou ,  Kou Tei

IPC: G11C11/56 ,  G11C11/4091 ,  G11C16/08 ,  H01L27/11 ,  G11C16/24 ,  G11C11/4074

Abstract: A storage device is disclosed herein. The storage device, comprises: a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines; and a reference current generator circuit configured to receive an input voltage from a voltage supply and generate therefrom a plurality of outputs, each output of the plurality of outputs used to generate one or more bias voltages/currents for one or more control signals. The control circuitry is configured to: receive a refresh read operation command; and adapt operation of the reference current generator circuit based on receiving the refresh read operation command. This proposal is also applicable for other test modes, such as SA stress, soft and preprogram, and SA test modes.

公开(公告)号：US11139022B1

公开(公告)日：2021-10-05

申请号：US16908467

申请日：2020-06-22

Applicant: SanDisk Technologies LLC

Inventor： Kou Tei ,  Ohwon Kwon ,  Jongyeon Kim ,  Chia-Kai Chou ,  Yuedan Li

IPC: G11C7/02 ,  G11C11/4091 ,  G11C11/4074 ,  G11C5/02 ,  G11C11/4096 ,  G11C11/4076

Abstract: An example of an apparatus includes a plurality of memory cells arranged in a plurality of NAND strings that are connected to a source line and a control circuit connected to the source line. The control circuit is configured to provide a first current to the source line to pre-charge the source line to a target voltage for sensing data states of the plurality of memory cells and provide a second current to the source line to return the source line to the target voltage in a recovery period between sensing data states. The control circuit is configured to provide the second current at any one of a plurality of current levels.

公开(公告)号：US10971209B1

公开(公告)日：2021-04-06

申请号：US16593576

申请日：2019-10-04

Applicant: SanDisk Technologies LLC

Inventor： Ohwon Kwon ,  Kou Tei ,  VSNK Chaitanya G

IPC: G11C11/4074 ,  G11C5/14 ,  G11C11/56 ,  G11C11/4091 ,  G11C11/4094

Abstract: A memory device is provided including physical block circuitry including a first lateral network arrangement and a second lateral network arrangement. Each of the first and second lateral network arrangements includes a single generator configured to output both a sense amplifier voltage VHSA and a data latch voltage VDDSA, in each of a first mode and a second mode. In the first mode, during which read and program verify and other operations may occur, the generator receives VHSA as a feedback signal and in the second mode, during which programming, POR, and EVFY operations may occur, the generator receives VDDSA as a feedback signal.

公开(公告)号：US20240331741A1

公开(公告)日：2024-10-03

申请号：US18346359

申请日：2023-07-03

Applicant: SanDisk Technologies LLC

Inventor： Iris Lu ,  Yonggang Wu ,  Kou Tei ,  Ohwon Kwon

IPC: G11C7/10 ,  G11C7/12

CPC classification number: G11C7/1048 ,  G11C7/1039 ,  G11C7/12

Abstract: Techniques are presented to reduce sense amplifier noise from parasitic capacitances that can affect the internal transfer of a data value from a data latch to a sensing node. To transfer the data value, the sensing node is pre-charged and the data value used to set the control gate voltage on a transistor in a discharge path for the sensing node. In the discharge path, the transistor is connected in series with a switch, so that when the switch is turned on, the data value on the transistor's control gate will determine whether or not the sensing node discharges. To reduce noise in the process, before the data value is used to bias the discharge path transistor's control gate, a node between the transistor and switch is charged. Additionally, a lower voltage level can be used to turn on the discharge path switch.