公开(公告)号：US20160104729A1

公开(公告)日：2016-04-14

申请号：US14840680

申请日：2015-08-31

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Laurent Favennec ,  Didier Dutartre ,  Francois Roy

IPC: H01L27/146

CPC classification number: H01L27/1462 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14685 ,  H01L27/14689 ,  H01L31/11 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of manufacturing a pinned photodiode, including: forming a region of photon conversion into electric charges of a first conductivity type on a substrate of the second conductivity type; coating said region with a layer of a heavily-doped insulator of the second conductivity type; and annealing to ensure a dopant diffusion from the heavily-doped insulator layer.

Abstract translation: 一种制造钉扎光电二极管的方法，包括：在第二导电类型的衬底上形成光子转换到第一导电类型的电荷的区域; 用第二导电类型的重掺杂绝缘体层涂覆所述区域; 和退火以确保掺杂剂从重掺杂绝缘体层扩散。

公开(公告)号：US09087872B2

公开(公告)日：2015-07-21

申请号：US14168167

申请日：2014-01-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent Favennec ,  Arnaud Tournier ,  François Roy

IPC: H01L21/762 ,  H01L27/146

CPC classification number: H01L21/76224 ,  H01L21/76237 ,  H01L27/1463

Abstract: A structure comprising at least one DTI-type insulating trench in a substrate, the trench being at the periphery of at least one active area of the substrate forming a pixel, the insulating trench including a cavity filled with a dielectric material, the internal walls of the cavity being covered with a layer made of a boron-doped material.

Abstract translation: 一种结构，其包括在衬底中的至少一个DTI型绝缘沟槽，所述沟槽位于形成像素的衬底的至少一个有源区域的外围，所述绝缘沟槽包括填充有电介质材料的腔体， 该腔被由硼掺杂材料制成的层覆盖。

公开(公告)号：US20140342524A1

公开(公告)日：2014-11-20

申请号：US14447699

申请日：2014-07-31

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Grégory Bidal ,  Laurent Favennec ,  Raul Andres Bianchi

IPC: H01L21/762 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/76232 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon.

Abstract translation: 一种集成电路，其包括限定由单晶半导体材料制成的有源区域的至少一个隔离沟槽，所述或每个沟槽包括上部，该上部包括封装沟槽的下部的绝缘层，所述下部至少部分地被埋置 在活性区域和包含氮或碳的包封层。

公开(公告)号：US20180090542A1

公开(公告)日：2018-03-29

申请号：US15452940

申请日：2017-03-08

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Emmanuel Gourvest ,  Yannick Le Friec ,  Laurent Favennec

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

Abstract: Two phase-change memory cells are formed from a first conductive via, a second conductive and a central conductive via positioned between the first and second conductive vias where a layer of phase-change material is electrically connected to the first and second conductive vias by corresponding resistive elements and insulated from the central conductive via by an insulating layer. The conductive vias each include a lower portion made of a first metal (such as tungsten) and an upper portion made of a second metal (such as copper). Drains of two transistors are coupled to the first and second conductive vias while sources of those two transistors are coupled to the central conductive via.

公开(公告)号：US09711550B2

公开(公告)日：2017-07-18

申请号：US14840680

申请日：2015-08-31

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Laurent Favennec ,  Didier Dutartre ,  Francois Roy

IPC: H01L27/146 ,  H01L31/11 ,  H01L31/18

CPC classification number: H01L27/1462 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14685 ,  H01L27/14689 ,  H01L31/11 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of manufacturing a pinned photodiode, including: forming a region of photon conversion into electric charges of a first conductivity type on a substrate of the second conductivity type; coating said region with a layer of a heavily-doped insulator of the second conductivity type; and annealing to ensure a dopant diffusion from the heavily-doped insulator layer.

公开(公告)号：US11653582B2

公开(公告)日：2023-05-16

申请号：US16184246

申请日：2018-11-08

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Arnaud ,  David Galpin ,  Stephane Zoll ,  Olivier Hinsinger ,  Laurent Favennec ,  Jean-Pierre Oddou ,  Lucile Broussous ,  Philippe Boivin ,  Olivier Weber ,  Philippe Brun ,  Pierre Morin

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H10N70/8616 ,  G11C13/0004 ,  G11C13/0069 ,  H10B63/30 ,  H10B63/80 ,  H10N70/011 ,  H10N70/021 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8265 ,  H10N70/8413 ,  H10N70/882 ,  G11C2013/008

Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.

公开(公告)号：US09117876B2

公开(公告)日：2015-08-25

申请号：US14447699

申请日：2014-07-31

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Grégory Bidal ,  Laurent Favennec ,  Raul Andres Bianchi

IPC: H01L21/336 ,  H01L21/762 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/76232 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon.

Abstract translation: 一种集成电路，其包括限定由单晶半导体材料制成的有源区域的至少一个隔离沟槽，所述或每个沟槽包括上部，该上部包括封装沟槽的下部的绝缘层，所述下部至少部分地被埋置 在活性区域和包含氮或碳的包封层。

公开(公告)号：US20140145251A1

公开(公告)日：2014-05-29

申请号：US14168167

申请日：2014-01-30

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Laurent Favennec ,  Arnaud Tournier ,  François Roy

IPC: H01L21/762 ,  H01L27/146

CPC classification number: H01L21/76224 ,  H01L21/76237 ,  H01L27/1463

Abstract: A structure comprising at least one DTI-type insulating trench in a substrate, the trench being at the periphery of at least one active area of the substrate forming a pixel, the insulating trench including a cavity filled with a dielectric material, the internal walls of the cavity being covered with a layer made of a boron-doped material.

Abstract translation: 一种结构，其包括在衬底中的至少一个DTI型绝缘沟槽，所述沟槽位于形成像素的衬底的至少一个有源区域的外围，所述绝缘沟槽包括填充有电介质材料的腔体， 该腔被由硼掺杂材料制成的层覆盖。

公开(公告)号：US12295272B2

公开(公告)日：2025-05-06

申请号：US17847016

申请日：2022-06-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent Favennec ,  Fausto Piazza

IPC: H10N70/20 ,  H01L23/522 ,  H10B63/10 ,  H10N70/00

Abstract: A method for making a phase change memory includes a step of forming an array of phase change memory cells, with each cell being separated from neighboring cells in the same line of the array and from neighboring cells in the same column of the array, by the same first distance. The method further includes a step of etching one memory cell out of N, with N being at least equal to 2, in each line or each column.

公开(公告)号：US12232435B2

公开(公告)日：2025-02-18

申请号：US18130184

申请日：2023-04-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Arnaud ,  David Galpin ,  Stephane Zoll ,  Olivier Hinsinger ,  Laurent Favennec ,  Jean-Pierre Oddou ,  Lucile Broussous ,  Philippe Boivin ,  Olivier Weber ,  Philippe Brun ,  Pierre Morin

IPC: H10B63/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.