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1.发明申请SYSTEM FOR DRIVING AN ARRAY OF MEMS STRUCTURES AND CORRESPONDING DRIVING METHOD 有权用于驱动MEMS结构阵列和相应驱动方法的系统公开(公告)号：US20150344295A1
公开(公告)日：2015-12-03
申请号：US14675230
申请日：2015-03-31
Applicant: STMICROELECTRONICS S.R.L.
IPC: B81B7/00
CPC classification number: B81B7/008 , B81B3/00 , B81B7/04 , B81B2201/0257 , B81B2207/03 , B81B2207/053 , H04R3/007 , H04R3/12 , H04R19/005 , H04R2201/003
Abstract: A system for driving a MEMS array having a number of MEMS structures, each defining at least one row terminal and one column terminal, envisages: a number of row driving stages, each for supplying row-biasing signals to the row terminal of each MEMS structure associated to a respective row; a number of column driving stages, each for supplying column-biasing signals to the column terminal of each MEMS structure associated to a respective column; and a control unit, for supplying row-address signals to the row driving stages for generation of the row-biasing signals and for supplying column-address signals to the column driving stages for generation of the column-biasing signals. The control unit further supplies row-deactivation and/or column-deactivation signals to one or more of the row and column driving stages, for causing deactivation of one or more rows and/or columns of the MEMS array.
Abstract translation: 用于驱动具有多个MEMS结构的MEMS阵列的系统，每个MEMS结构限定至少一个行端子和一个列端子，设想：多个行驱动级，每个用于向每个MEMS结构的行端子提供行偏置信号 相关联的行; 多个列驱动级，每个列驱动级用于向与各列相关联的每个MEMS结构的列端子提供列偏置信号; 以及控制单元，用于将行地址信号提供到行驱动级，用于产生行偏置信号，并将列地址信号提供给列驱动级，以产生列偏置信号。 控制单元还向行驱动级和列驱动级中的一个或多个驱动级提供行去激活和/或列停用信号，以使MEMS阵列的一个或多个行和/或列的去激活。
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公开(公告)号：US20230299670A1
公开(公告)日：2023-09-21
申请号：US18121767
申请日：2023-03-15
Applicant: STMicroelectronics S.r.l.
Inventor： Alberto CATTANI , Alessandro GASPARINI , Stefano RAMORINI
CPC classification number: H02M3/156 , H02M1/0003
Abstract: A switching DC-DC converter circuit includes a switching stage having an input node receiving an input voltage and an output node producing an output voltage. The converter includes feedback loop circuitry coupled to the output node of the switching stage to produce, at a respective output node, a control signal of the converter circuit as a function of a difference between the output voltage and a reference voltage. The converter includes test loop circuitry arranged between an output node of the feedback loop circuitry and the output node of the switching stage. The test loop, when enabled, sources a current to the output node of the switching stage or sinks a current from the output node of the switching stage as a function of a value of the control signal of the converter circuit. The feedback loop circuitry is calibrated during a test phase of the switching DC-DC converter circuit.
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3.发明公开公开(公告)号：US20230163767A1
公开(公告)日：2023-05-25
申请号：US17982712
申请日：2022-11-08
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro BERTOLINI , Alberto CATTANI , Alessandro GASPARINI
CPC classification number: H03L7/0991 , H03L7/091 , H03L7/10
Abstract: In a control circuit for a switching stage of an electronic converter, a phase detector generates a drive signal in response to a phase difference between first and second clock signals. The first and second clock signals are generated by first and second current-controlled oscillators, respectively. An operational transconductance amplifier generates first and second control currents in response to a difference between a reference and a feedback of the electronic converter, with the first and second currents applied to control the first and second current-controlled oscillators. In response to a switching clock having a first state, a switching circuit applies first and second bias currents to the control inputs of the first and second current-controlled oscillators, respectively. Conversely, in response to the switching clock having a second state, the switching circuit applies the second and first bias currents to the control inputs of the first and second current-controlled oscillators, respectively.
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公开(公告)号：US20230128113A1
公开(公告)日：2023-04-27
申请号：US17964420
申请日：2022-10-12
Applicant: STMicroelectronics S.r.l.
Inventor： Marco PINSERO , Marco ATTANASIO , Alberto CATTANI
IPC: H03K4/50
Abstract: In start-up, current is sourced by a current source to a first plate of a first capacitor while a second capacitor is maintained at zero charge. In a subsequent first operating phase, current is sourced to a first plate of the second capacitor while a second plate of the first capacitor is connected to the first plate of the second capacitor. At the end of the first operating phase, the first capacitor is discharged. In a subsequent second operating phase, current is sourced to the first plate of the first capacitor while a second plate of the second capacitor is connected to the first plate of the first capacitor. At the end of the second operating phase, the second capacitor is discharged. Steady state operation of the circuit involves an alternation of the first and second operating phases interleaved with transition phases where the first and second capacitors are discharged.
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公开(公告)号：US20210099087A1
公开(公告)日：2021-04-01
申请号：US17122132
申请日：2020-12-15
Applicant: STMicroelectronics S.r.l.
Inventor： Alberto CATTANI , Stefano RAMORINI , Alessandro GASPARINI
IPC: H02M3/158
Abstract: A half-bridge converter is controlled by a circuit including a differential circuit receiving a reference signal and a feedback signal which is a function of an output signal from the converter. The half-bridge converter includes high-side and low-side electronic switches. A comparator generates a PWM-modulated signal for controlling the converter as a function of the duty cycle of the PWM-modulated signal in response to a signal at an intermediate node between the high-side and low-side electronic switches and an output of the differential circuit. A gain circuit block coupled between the intermediate node and the input of the comparator applies a ramp signal to the input of the comparator which is a function of the signal at the intermediate node. A variable gain is applied by the gain circuit block in order to keep a constant value for the duty cycle of said PWM-modulated signal irrespective of converter operation.
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Patent Agency Ranking
公开(公告)号：US20210067148A1
公开(公告)日：2021-03-04
申请号：US16559118
申请日：2019-09-03
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro BERTOLINI , Alberto CATTANI , Stefano RAMORINI , Alessandro GASPARINI
Abstract: A DC-DC converter includes clock generation circuitry generating first and second clock signals that are out of phase, and a control signal generator generating a switching control signal at an edge of the second clock signal based upon a comparison of an error voltage to a summed voltage. Boost circuitry charges an energy storage component during an on-phase and discharges the energy storage component during an off-phase to thereby generate an output voltage. The on-phase and off-phase are set as a function of the switching control signal. Sum voltage generation circuitry generates a ramp voltage in response to an edge of the first clock signal and generates the summed voltage at an edge of the second clock signal. The sum voltage represents a sum of the ramp voltage and a voltage representative of the current flowing in the energy storage component during the on-phase.
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公开(公告)号：US20220166315A1
公开(公告)日：2022-05-26
申请号：US17533338
申请日：2021-11-23
Applicant: STMicroelectronics S.r.l.
Inventor： Stefano RAMORINI , Alessandro GASPARINI , Alberto CATTANI
IPC: H02M3/07
Abstract: Charge pump stages are coupled between flying capacitor pairs and arranged in a cascaded between a bottom voltage line and an output voltage line. Gain stages apply pump phase signals having a certain amplitude to the charge pump stages via the flying capacitors. A feedback signal path from the output voltage line to the bottom voltage line applies a feedback control signal to the bottom voltage line. Power supply for the gain stages is provided by a voltage of the feedback control signal in order to control the amplitude of the pump phase signals. An asynchronous logic circuit generates the switching drive signals for the gain stages with a certain switching frequency which is a function of a logic supply voltage derived from the voltage of the feedback control signal.
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公开(公告)号：US20210074835A1
公开(公告)日：2021-03-11
申请号：US16561670
申请日：2019-09-05
Applicant: STMicroelectronics S.r.l.
Inventor： Alberto CATTANI , Alessandro GASPARINI
IPC: H01L29/739 , H02M1/32 , H02M3/158
Abstract: A power MOS stage includes a first power MOS device and a second power MOS devices connected in parallel between a first node and a second node, the first power MOS device having a first voltage rating and the second power MOS device having a second voltage rating that is lower than the first voltage rating. A driver circuit is configured to drive control nodes of the first and second power MOS devices in a sequential manner when actuating the power MOS stage by actuating the first power MOS device before actuating the second power MOS device. The control nodes of the first and second power MOS devices are further driven in a sequential manner when deactuating the power MOS stage by deactuating the second power MOS device before deactuating the first power MOS device.
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公开(公告)号：US20190372535A1
公开(公告)日：2019-12-05
申请号：US16539478
申请日：2019-08-13
Applicant: STMicroelectronics S.r.l.
Inventor： Stefano RAMORINI , Alberto CATTANI , Germano NICOLLINI , Alessandro GASPARINI
Abstract: A switching amplifier, such as a Class D amplifier, includes a current sensing circuit. The current sensing circuit is formed by replica loop circuits that are selectively coupled to corresponding output inverter stages of the switching amplifier. The replica loop circuits operated to produce respective replica currents of the output currents generated by the output inverter stages. A sensing circuitry is coupled to receive the replica currents from the replica loop circuits and operates to produce an output sensing signal as a function of the respective replica currents.
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公开(公告)号：US20180337647A1
公开(公告)日：2018-11-22
申请号：US15982548
申请日：2018-05-17
Applicant: STMicroelectronics S.r.l.
Inventor： Stefano RAMORINI , Alberto CATTANI , Alessandro GASPARINI , Germano NICOLLINI
CPC classification number: H03F3/45192 , H03F2200/18 , H03M1/124 , H03M1/66 , H03M1/68 , H03M1/742 , H03M1/765
Abstract: A circuit includes an input transistor pair with first and second input transistors, the first input transistor having a control terminal configured to receive an input signal and a cascode transistor pair including a first and second cascode transistors having a common control node. A bias circuit has a bias input configured to receive the input signal and a first bias output coupled to the common node of the first and second cascode transistors. The bias circuit includes a signal tracking circuit operating to generate the first bias output to track the input signal. A pair of load transistors are coupled to the input transistor pair and biased by a second bias output of the bias circuit.
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