公开(公告)号：US10032803B2

公开(公告)日：2018-07-24

申请号：US15343780

申请日：2016-11-04

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Zhu Xun ,  Jae Woo Park ,  Jae Won Song ,  Keum Hee Lee ,  June Whan Choi

IPC: H01L21/00 ,  H01L31/00 ,  H01L27/12 ,  H01L29/417 ,  H01L21/443 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H01L21/768 ,  H01L23/532 ,  G02F1/1335 ,  G02F1/1368

Abstract: A thin film transistor array panel is provided as follows. A gate electrode is disposed on a substrate. A semiconductor layer is disposed on the gate electrode. A gate insulating layer is disposed between the gate electrode and the semiconductor layer. A source electrode is disposed on a first side of the semiconductor layer, having a first lateral surface. A drain electrode is disposed on a second side of the semiconductor layer, having a second lateral surface. The first and second lateral surfaces define a spacing which overlaps the gate electrode. A metal suicide layer is disposed on the first and second lateral surfaces. A passivation layer is disposed on the metal silicide layer, the source electrode and the drain electrode. The passivation layer is not in contact with the first and second lateral surfaces.

公开(公告)号：US09823531B2

公开(公告)日：2017-11-21

申请号：US14277526

申请日：2014-05-14

Applicant: Samsung Display Co., Ltd.

Inventor： Tae-Young Choi ,  Bo Sung Kim ,  Jae Woo Park ,  Hee Jun Byeon ,  Young-Wook Lee ,  Moon-Keun Choi

IPC: G02F1/1362 ,  H01L27/12 ,  H01L27/02

CPC classification number: G02F1/136286 ,  G02F1/136204 ,  H01L27/0288 ,  H01L27/124

Abstract: A thin film transistor array panel includes: gate lines; data lines insulated from and crossing the gate lines; and shorting bars disposed outside of a display area in which the gate lines cross the data lines. The shorting bars overlap portions of the data lines disposed outside of the display area. The shorting bar includes a semiconductor material.

公开(公告)号：US09515093B2

公开(公告)日：2016-12-06

申请号：US14466317

申请日：2014-08-22

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Zhu Xun ,  Jae Woo Park ,  Jae Won Song ,  Keum Hee Lee ,  June Whan Choi

IPC: H01L29/12 ,  H01L29/10 ,  H01L27/12 ,  H01L29/417 ,  H01L21/443 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L27/124 ,  G02F1/133512 ,  G02F1/133514 ,  G02F1/1368 ,  G02F2001/133519 ,  G02F2201/121 ,  G02F2201/123 ,  H01L21/443 ,  H01L21/76852 ,  H01L23/53238 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66765 ,  H01L29/78618 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thin film transistor array panel is provided as follows. A gate electrode is disposed on a substrate. A semiconductor layer is disposed on the gate electrode. A gate insulating layer is disposed between the gate electrode and the semiconductor layer. A source electrode is disposed on a first side of the semiconductor layer, having a first lateral surface. A drain electrode is disposed on a second side of the semiconductor layer, having a second lateral surface. The first and second lateral surfaces define a spacing which overlaps the gate electrode. A metal silicide layer is disposed on the first and second lateral surfaces. A passivation layer is disposed on the metal silicide layer, the source electrode and the drain electrode. The passivation layer is not in contact with the first and second lateral surfaces.

Abstract translation: 如下提供薄膜晶体管阵列面板。 栅电极设置在基板上。 半导体层设置在栅电极上。 栅极绝缘层设置在栅电极和半导体层之间。 源电极设置在半导体层的第一侧上，具有第一侧表面。 漏电极设置在半导体层的第二侧上，具有第二侧表面。 第一和第二侧表面限定了与栅电极重叠的间隔。 金属硅化物层设置在第一和第二侧表面上。 在金属硅化物层，源电极和漏电极上设置钝化层。 钝化层不与第一和第二侧表面接触。

公开(公告)号：US09245906B2

公开(公告)日：2016-01-26

申请号：US14795431

申请日：2015-07-09

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jae Woo Park ,  Do-Hyun Kim ,  Young Joo Choi ,  Dong Hoon Lee ,  Sung Haeng Cho

IPC: H01L29/10 ,  H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, and a data wire layer disposed on the substrate and including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode. In addition, at least one of the data line, the source electrode or the drain electrode of the data wire layer includes a barrier layer and a main wiring layer disposed on the barrier layer. The main wiring layer includes copper or a copper alloy. Also, the barrier layer includes a metal oxide, and the metal oxide includes zinc.

公开(公告)号：US09188867B2

公开(公告)日：2015-11-17

申请号：US14016748

申请日：2013-09-03

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Byung Du Ahn ,  Seung Ho Yeon ,  Sei-Yong Park ,  Mi-Hyae Park ,  Bu Sop Song ,  Tae Gweon Lee ,  Jun Hyun Park ,  Je Hun Lee ,  Jae Woo Park

IPC: H01L29/10 ,  G03F7/075 ,  H01L23/29 ,  C08L83/04 ,  H01L29/51 ,  G02F1/1362 ,  G03F7/16 ,  G03F7/20 ,  C08G77/16 ,  C08G77/20 ,  C08G77/00 ,  H01L27/32 ,  H01L27/12

CPC classification number: G03F7/0757 ,  C08G77/16 ,  C08G77/20 ,  C08G77/80 ,  C08L83/04 ,  G02F1/136227 ,  G03F7/16 ,  G03F7/20 ,  H01L23/296 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1288 ,  H01L27/3258 ,  H01L29/517 ,  H01L2924/0002 ,  C08L83/00 ,  H01L2924/00

Abstract: A passivation layer solution composition is provided. A passivation layer solution composition according to an exemplary embodiment of the present invention includes an organic siloxane resin represented by Chemical Formula 1 below. In Chemical Formula 1, R is at least one substituent selected from a saturated hydrocarbon or an unsaturated hydrocarbon having from 1 to about 25 carbon atoms, and x and y may each independently be from 1 to about 200, and wherein each wavy line indicates a bond to an H atom or to an x siloxane unit or a y siloxane unit, or a bond to an x siloxane unit or a y siloxane unit of another siloxane chain comprising x siloxane units or y siloxane units or a combination thereof.

Abstract translation: 提供钝化层溶液组合物。 根据本发明的示例性实施方案的钝化层溶液组合物包括由下述化学式1表示的有机硅氧烷树脂。 在化学式1中，R是选自饱和烃或具有1至约25个碳原子的不饱和烃中的至少一个取代基，x和y各自独立地为1至约200，并且其中每个波浪线表示 键合到H原子或x硅氧烷单元或硅氧烷单元，或与包含x硅氧烷单元或y硅氧烷单元或其组合的另一硅氧烷链的x硅氧烷单元或硅氧烷单元的键。

公开(公告)号：US20150050597A1

公开(公告)日：2015-02-19

申请号：US14525688

申请日：2014-10-28

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Byung Du Ahn ,  Seung Ho Yeon ,  Sei-Yong Park ,  Mi-Hyae Park ,  Bu Sop Song ,  Tae Gweon Lee ,  Jun Hyun Park ,  Je Hun Lee ,  Jae Woo Park

IPC: G03F7/075 ,  G03F7/20 ,  H01L27/12 ,  G03F7/16

CPC classification number: G03F7/0757 ,  C08G77/16 ,  C08G77/20 ,  C08G77/80 ,  C08L83/04 ,  G02F1/136227 ,  G03F7/16 ,  G03F7/20 ,  H01L23/296 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1288 ,  H01L27/3258 ,  H01L29/517 ,  H01L2924/0002 ,  C08L83/00 ,  H01L2924/00

Abstract: A passivation layer solution composition is provided A passivation layer solution composition according to an exemplary embodiment of the present invention includes an organic siloxane resin represented by Chemical Formula 1 below. In Chemical Formula 1, R is at least one substituent selected from a saturated hydrocarbon or an unsaturated hydrocarbon having from 1 to about 25 carbon atoms, and x and y may each independently be from 1 to about 200, and wherein each wavy line indicates a bond to an H atom or to an x siloxane unit or a y siloxane unit, or a bond to an x siloxane unit or a y siloxane unit of another siloxane chain comprising x siloxane units or y siloxane units or a combination thereof.

Abstract translation: 提供钝化层溶液组合物根据本发明示例性实施方案的钝化层溶液组合物包括由下述化学式1表示的有机硅氧烷树脂。 在化学式1中，R是选自饱和烃或具有1至约25个碳原子的不饱和烃中的至少一个取代基，x和y各自独立地为1至约200，并且其中每个波浪线表示 键合到H原子或x硅氧烷单元或硅氧烷单元，或与包含x硅氧烷单元或y硅氧烷单元或其组合的另一硅氧烷链的x硅氧烷单元或硅氧烷单元的键。

公开(公告)号：US10256091B2

公开(公告)日：2019-04-09

申请号：US15290715

申请日：2016-10-11

Applicant: Kobe Steel, Ltd. ,  Samsung Display Co., Ltd.

Inventor： Hiroaki Tao ,  Aya Miki ,  Shinya Morita ,  Satoshi Yasuno ,  Toshihiro Kugimiya ,  Jae Woo Park ,  Je Hun Lee ,  Byung Du Ahn ,  Gun Hee Kim

IPC: H01L21/00 ,  H01L21/02 ,  H01L29/786 ,  H01L29/12 ,  H01L29/66 ,  H01L21/477 ,  G02F1/1368

Abstract: The oxide of the present invention for thin-film transistors is an In—Zn—Sn-based oxide containing In, Zn, and Sn, wherein when the respective contents (atomic %) of metal elements contained in the In—Zn—Sn-based oxide are expressed by [Zn], [Sn], and [In], the In—Zn—Sn-based oxide fulfills the following expressions (2) and (4) when [In]/([In]+[Sn])≤0.5; or the following expressions (1), (3), and (4) when [In]/([In]+[Sn])>0.5. [In]/([In]+[Zn]+[Sn])≤0.3  (1), [In]/([In]+[Zn]+[Sn])≤1.4×{[Zn]/([Zn]+[Sn])}−0.5  (2), [Zn]/([In]+[Zn]+[Sn])≤0.83  (3), and 0.1≤[In]/([In]+[Zn]+[Sn])  (4). According to the present invention, oxide thin films for thin-film transistors can be obtained, which provide TFTs with excellent switching characteristics, and which have high sputtering rate in the sputtering and properly controlled etching rate in the wet etching.

公开(公告)号：US09470978B2

公开(公告)日：2016-10-18

申请号：US14525688

申请日：2014-10-28

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Byung Du Ahn ,  Seung Ho Yeon ,  Sei-Yong Park ,  Mi-Hyae Park ,  Bu Sop Song ,  Tae Gweon Lee ,  Jun Hyun Park ,  Je Hun Lee ,  Jae Woo Park

IPC: G03F7/075 ,  H01L23/29 ,  C08L83/04 ,  H01L29/51 ,  G02F1/1362 ,  G03F7/16 ,  G03F7/20 ,  C08G77/16 ,  C08G77/20 ,  C08G77/00 ,  H01L27/32 ,  H01L27/12

CPC classification number: G03F7/0757 ,  C08G77/16 ,  C08G77/20 ,  C08G77/80 ,  C08L83/04 ,  G02F1/136227 ,  G03F7/16 ,  G03F7/20 ,  H01L23/296 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1288 ,  H01L27/3258 ,  H01L29/517 ,  H01L2924/0002 ,  C08L83/00 ,  H01L2924/00

Abstract: A passivation layer solution composition is provided. A passivation layer solution composition according to an exemplary embodiment of the present invention includes an organic siloxane resin represented by Chemical Formula 1 below. In Chemical Formula 1, R is at least one substituent selected from a saturated hydrocarbon or an unsaturated hydrocarbon having from 1 to about 25 carbon atoms, and x and y may each independently be from 1 to about 200, and wherein each wavy line indicates a bond to an H atom or to an x siloxane unit or a y siloxane unit, or a bond to an x siloxane unit or a y siloxane unit of another siloxane chain comprising x siloxane units or y siloxane units or a combination thereof.

公开(公告)号：US09142680B2

公开(公告)日：2015-09-22

申请号：US13725333

申请日：2012-12-21

Applicant: Samsung Display Co., Ltd.

Inventor： Hye Young Ryu ,  Ki Won Kim ,  Jae Woo Park ,  Kap Soo Yoon ,  Young Joo Choi

IPC: H01L29/04 ,  H01L29/10 ,  H01L29/786 ,  H01L33/08 ,  H01L27/12

CPC classification number: H01L29/786 ,  H01L27/1225 ,  H01L27/124 ,  H01L33/08

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate line positioned on the substrate; a gate insulating layer positioned on the gate line; a semiconductor layer positioned on the gate insulating layer and having a channel portion; a data line including a source electrode and a drain electrode, the source and drain electrodes both positioned on the semiconductor layer; a passivation layer positioned on the data line and the drain electrode and having a contact hole formed therein; and a pixel electrode positioned on the passivation layer, wherein the pixel electrode contacts the drain electrode within the contact hole, and the channel portion of the semiconductor layer and the contact hole both overlap the gate line in a plan view of the substrate.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：基板; 位于基板上的栅极线; 位于栅极线上的栅极绝缘层; 位于所述栅极绝缘层上且具有沟道部分的半导体层; 包括源电极和漏电极的数据线，所述源极和漏极都位于所述半导体层上; 位于数据线和漏电极上并具有形成在其中的接触孔的钝化层; 位于所述钝化层上的像素电极，其中所述像素电极在所述接触孔内接触所述漏电极，并且所述半导体层的沟道部分和所述接触孔在所述衬底的平面图中与所述栅极线重叠。

公开(公告)号：US09099438B2

公开(公告)日：2015-08-04

申请号：US13660362

申请日：2012-10-25

Applicant: Samsung Display Co., Ltd.

Inventor： Jae Woo Park ,  Do-Hyun Kim ,  Young Joo Choi ,  Dong Hoon Lee ,  Sung Haeng Cho

IPC: H01L29/10 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, and a data wire layer disposed on the substrate and including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode. In addition, at least one of the data line, the source electrode or the drain electrode of the data wire layer includes a barrier layer and a main wiring layer disposed on the barrier layer. The main wiring layer includes copper or a copper alloy. Also, the barrier layer includes a metal oxide, and the metal oxide includes zinc.

Abstract translation: 薄膜晶体管阵列面板包括：栅极线，设置在基板上并且包括栅电极，包括设置在基板上的氧化物半导体的半导体层以及设置在基板上的数据线层，并且包括与栅极交叉的数据线 线，连接到数据线的源电极和面对源电极的漏电极。 此外，数据线层的数据线，源电极或漏电极中的至少一个包括阻挡层和设置在阻挡层上的主配线层。 主配线层包括铜或铜合金。 此外，阻挡层包括金属氧化物，并且金属氧化物包括锌。