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    PROXIMITY CORRECTION METHODS FOR SEMICONDUCTOR MANUFACTURING PROCESSES
    3.
    发明申请
    PROXIMITY CORRECTION METHODS FOR SEMICONDUCTOR MANUFACTURING PROCESSES 有权

    公开(公告)号：US20210405521A1

    公开(公告)日：2021-12-30

    申请号：US17180984

    申请日：2021-02-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taehoon Kim ,  Jaeho Jeong ,  Jeonghoon Ko ,  Jongwon Kim ,  Yejin Jeong ,  Changwook Jeong

    IPC: G03F1/36 ,  G03F7/20 ,  H01L21/027

    Abstract: A proximity correction method for a semiconductor manufacturing process includes: generating a plurality of pieces of original image data from a plurality of sample regions, with the sample regions selected from layout data used in the semiconductor manufacturing process; removing some pieces of original image data that overlap with each other from the plurality of pieces of original image data, resulting in a plurality of pieces of input image data; inputting the plurality of pieces of input image data to a machine learning model; obtaining a prediction value of critical dimensions of target patterns included in the plurality of pieces of input image data from the machine learning model; measuring a result value for critical dimensions of actual patterns corresponding to the target patterns on a semiconductor substrate on which the semiconductor manufacturing process is performed; and performing learning of the machine learning model using the prediction value and the result value.

    ELECTRONIC DEVICES GENERATING VERIFICATION VECTOR FOR VERIFYING SEMICONDUCTOR CIRCUIT AND METHODS OF OPERATING THE SAME
    4.
    发明申请
    ELECTRONIC DEVICES GENERATING VERIFICATION VECTOR FOR VERIFYING SEMICONDUCTOR CIRCUIT AND METHODS OF OPERATING THE SAME 有权

    公开(公告)号：US20210117193A1

    公开(公告)日：2021-04-22

    申请号：US16915786

    申请日：2020-06-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seungju Kim ,  Hyojin Choi ,  In Huh ,  Jeonghoon Ko ,  Changwook Jeong ,  Younsik Park ,  Joonwan Chai

    IPC: G06F9/30 ,  G06N20/00 ,  G06F9/38 ,  G06K9/62

    Abstract: An electronic device configured to generate a verification vector for verifying a semiconductor circuit including a first circuit block and a second circuit block includes a duplicate command eliminator configured to receive a first input vector including a plurality of commands and to provide a first converted vector, in which ones of the plurality of commands that generate the same state transition are changed into idle commands, based on a state transition of the first circuit block obtained by performing a simulation operation on the first input vector, a reduced vector generator configured to provide a first reduced vector in which a number of repetitions of the idle commands included in the first converted vector is reduced, and a verification vector generator configured to output the first reduced vector having a coverage that coincides with a target coverage among a plurality of first reduced vectors as a first verification vector.

    SYSTEM AND METHOD FOR MODELING A SEMICONDUCTOR FABRICATION PROCESS
    7.
    发明申请
    SYSTEM AND METHOD FOR MODELING A SEMICONDUCTOR FABRICATION PROCESS 有权

    公开(公告)号：US20220092239A1

    公开(公告)日：2022-03-24

    申请号：US17231428

    申请日：2021-04-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunjoong Kim ,  Jaepil Shin ,  Moonhyun Cha ,  Changwook Jeong

    IPC: G06F30/27 ,  G06N3/08 ,  G06N3/04

    Abstract: A system for modeling a semiconductor fabrication process includes at least one first processor and at least one second processor. The at least one first processor is configured to provide at least one machine learning (ML) model, which is trained by using a plurality of pairs of images of a design pattern sample and a physical pattern sample. The physical pattern sample is formed from the design pattern sample by using the semiconductor fabrication process. The at least one second processor is configured to provide an input image representing a shape of a design pattern and/or a physical pattern to the at least one first processor and to generate output data defining the physical pattern and/or the design pattern based on an output image received from the at least one first processor.

    Proximity correction methods for semiconductor manufacturing processes
    9.
    发明授权
    Proximity correction methods for semiconductor manufacturing processes 有权

    公开(公告)号：US11733603B2

    公开(公告)日：2023-08-22

    申请号：US17180984

    申请日：2021-02-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taehoon Kim ,  Jaeho Jeong ,  Jeonghoon Ko ,  Jongwon Kim ,  Yejin Jeong ,  Changwook Jeong

    IPC: G03F1/36 ,  H01L21/027 ,  G03F7/20 ,  G03F7/00

    CPC classification number: G03F1/36 ,  G03F7/70441 ,  G03F7/70625 ,  H01L21/027

    Abstract: A proximity correction method for a semiconductor manufacturing process includes: generating a plurality of pieces of original image data from a plurality of sample regions, with the sample regions selected from layout data used in the semiconductor manufacturing process; removing some pieces of original image data that overlap with each other from the plurality of pieces of original image data, resulting in a plurality of pieces of input image data; inputting the plurality of pieces of input image data to a machine learning model; obtaining a prediction value of critical dimensions of target patterns included in the plurality of pieces of input image data from the machine learning model; measuring a result value for critical dimensions of actual patterns corresponding to the target patterns on a semiconductor substrate on which the semiconductor manufacturing process is performed; and performing learning of the machine learning model using the prediction value and the result value.

    Simulation system for semiconductor process and simulation method thereof
    10.
    发明授权
    Simulation system for semiconductor process and simulation method thereof 有权

    公开(公告)号：US11574095B2

    公开(公告)日：2023-02-07

    申请号：US16906038

    申请日：2020-06-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sanghoon Myung ,  Hyunjae Jang ,  In Huh ,  Hyeon Kyun Noh ,  Min-Chul Park ,  Changwook Jeong

    IPC: G06F30/27 ,  G06N3/08 ,  G06N3/10 ,  G06N3/04 ,  G06F30/398

    Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

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