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1.发明申请公开(公告)号：US20240414926A1
公开(公告)日：2024-12-12
申请号：US18813539
申请日：2024-08-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wooyoung YANG , Bonwon KOO , Chungman KIM , Kwangmin PARK , Hajun SUNG , Dongho AHN , Changseung LEE , Minwoo CHOI
Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).
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公开(公告)号：US20240065001A1
公开(公告)日：2024-02-22
申请号：US18299403
申请日：2023-04-12
Applicant: SAMSUNG ELECTRONICS CO,LTD.
Inventor： Seyun KIM , Jooheon KANG , Sunho KIM , Yumin KIM , Garam PARK , Hyunjae SONG , Dongho AHN , Seungyeul YANG , Myunghun WOO , Jinwoo LEE
IPC: H10B63/00
CPC classification number: H10B63/845 , H10B63/34
Abstract: Provided area a variable resistance memory device and/or an electronic device including the same. The variable resistance memory device includes: a resistance change layer including a metal oxide having an oxygen deficient ratio greater than or equal to about 9%; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and a plurality of electrodes on the gate insulating layer to be apart from each other.
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公开(公告)号：US20220085286A1
公开(公告)日：2022-03-17
申请号：US17384933
申请日：2021-07-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jeonghee PARK , Dongho AHN , Wonjun PARK
Abstract: A semiconductor device includes a first conductive line on a lower structure and extending in a first horizontal direction; a second conductive line on the first conductive line and extending in a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction; and a memory cell structure between the first conductive line and the second conductive line. The memory cell may structure include a data storage material pattern and a selector material pattern overlapping the data storage material pattern in a vertical direction. The data storage material pattern may include a phase change material layer of InαGeβSbγTeδ. In the phase change material layer of InαGeβSbγTeδ, a sum of α and β may be lower than about 30 at. %, and a sum of γ and δ may be higher than about 70 at. %.
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公开(公告)号：US20230354725A1
公开(公告)日：2023-11-02
申请号：US18349433
申请日：2023-07-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kiyeon YANG , Dongho AHN , Changseung LEE
CPC classification number: H10N70/8828 , H10B63/24 , H10B63/84 , H10N70/066 , H10N70/231 , H10N70/8413
Abstract: A semiconductor apparatus may include a plurality of semiconductor unit devices. Each of the semiconductor unit devices may be arranged between a first insulating layer and a second insulating layer that are apart from each other in a direction normal to a substrate. Each of the semiconductor unit devices may include a selection device layer and a phase change material layer that extend side by side in a direction parallel to the substrate. The phase change material layer may have a superlattice-like structure. The phase change material layer may be arranged along a recess portion that is formed by the first insulating layer, the second insulating layer, and the selection device layer.
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5.发明申请公开(公告)号：US20230091136A1
公开(公告)日：2023-03-23
申请号：US17835508
申请日：2022-06-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kiyeon YANG , Segab KWON , Hajun SUNG , Dongho AHN , Changseung LEE
Abstract: Provided are a chalcogenide-based material, and a switching element and a memory device that include the same. The chalcogenide-based material includes: a chalcogenide material and a dopant. The chalcogenide material includes Ge, Sb, and Se. The dopant includes at least one metal or metalloid element selected from In, Al, Sr, and Si, an oxide of the metal or metalloid element, or a nitride of the metal or metalloid element.
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Patent Agency Ranking
公开(公告)号：US20220173316A1
公开(公告)日：2022-06-02
申请号：US17330950
申请日：2021-05-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kiyeon YANG , Dongho AHN , Changseung LEE
Abstract: Provided is a semiconductor apparatus including a plurality of semiconductor unit devices. Each of the semiconductor unit devices may be arranged between a first insulating layer and a second insulating layer that are apart from each other in a direction normal to a substrate. Each of the semiconductor unit devices may include a selection device layer and a phase change material layer that extend side by side in a direction parallel to the substrate. The phase change material layer may have a superlattice-like structure. The phase change material layer may be arranged along a recess portion that is formed by the first insulating layer, the second insulating layer, and the selection device layer.
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公开(公告)号：US20220069011A1
公开(公告)日：2022-03-03
申请号：US17209660
申请日：2021-03-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongho AHN , Segab KWON , Chungman KIM , Kwangmin PARK , Zhe WU , Seunggeun YU , Wonjun LEE , Jabin LEE , Jinwoo LEE
Abstract: A semiconductor device includes a semiconductor substrate, a peripheral device on the semiconductor substrate, a lower insulating structure on the semiconductor substrate and covering the peripheral device, a first conductive line on the lower insulating structure, a memory cell structure on the first conductive line, and a second conductive line on the memory cell structure. The memory cell structure may include an information storage material pattern and a selector material pattern on the lower insulating structure in a vertical direction. The selector material pattern may include a first selector material layer including a first material and a second selector material layer including a second material. The second selector material layer may have a threshold voltage drift higher than that of the first material. The second selector material layer may have a second width narrower than a first width of the first selector material layer.
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公开(公告)号：US20240324246A1
公开(公告)日：2024-09-26
申请号：US18594355
申请日：2024-03-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kiyeon YANG , Donggeon GU , Bonwon KOO , Jeonghee PARK , Hajun SUNG , Dongho AHN , Zhe WU , Changseung LEE , Minwoo CHOI
CPC classification number: H10B63/24 , H10B63/84 , H10N70/841 , H10N70/8825 , H10N70/8828
Abstract: Provided are a self-selecting memory device having polarity dependent threshold voltage shift characteristics and/or a memory apparatus including the self-selecting memory device. The memory device includes a first electrode, a second electrode apart from and facing the first electrode, and a memory layer between the first electrode and the second electrode. The memory layer has Ovonic threshold switching characteristics and is configured to have a threshold voltage of the memory layer be changed as a density of active traps in the memory layer is changed, the threshold voltage changing according to the polarity and the intensity of a bias voltage applied to the memory layer. Furthermore, an element composition distribution is configured to be maintained constant in the memory layer in response to the threshold voltage of the memory layer changing.
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9.发明公开公开(公告)号：US20240032308A1
公开(公告)日：2024-01-25
申请号：US18478776
申请日：2023-09-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wooyoung YANG , Bonwon KOO , Chungman KIM , Kwangmin PARK , Hajun SUNG , Dongho AHN , Changseung LEE , Minwoo CHOI
CPC classification number: H10B63/24 , G11C13/0004 , H10B61/10 , H10B63/84 , H10N50/01 , H10N50/80 , H10N70/24 , H10N70/25 , H10N70/063 , H10N70/231 , H10N70/8413 , H10N70/8825 , H10N70/8828 , H10N70/8833 , H10N70/8836
Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).
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公开(公告)号：US20230230832A1
公开(公告)日：2023-07-20
申请号：US18095243
申请日：2023-01-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Donggeon GU , Won-Jun LEE , Changyup PARK , Dongho AHN , Yewon KIM , Kwonyoung KIM , Okhyeon KIM
IPC: H01L21/02 , C23C16/455 , C23C16/06 , C23C16/56
CPC classification number: H01L21/02568 , H01L21/0262 , H01L21/02614 , C23C16/45527 , C23C16/06 , C23C16/56 , H10B63/10
Abstract: A method of forming a germanium antimony tellurium (GeSbTe) layer includes forming a germanium antimony (GeSb) layer by repeatedly performing a GeSb supercycle; and forming the GeSbTe layer by performing a tellurization operation on the GeSb layer, wherein the GeSb supercycle includes performing at least one GeSb cycle; and performing at least one Sb cycle, the GeSbTe has a composition of Ge2Sb2+aTe5+b, in which a and b satisfy the following relations: −0.2
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