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公开(公告)号：US20200349064A1
公开(公告)日：2020-11-05
申请号：US16934261
申请日：2020-07-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Gwangman LIM , Eun-Jin YUN
Abstract: A storage device includes nonvolatile memory devices, a connector that includes connection terminals, and a controller that communicates with an external host device through the connector and to control the nonvolatile memory devices. The connector provides the external host device with detection information in response to the connector being connected with the external host device. Power is supplied from the external host device to the controller and the nonvolatile memory devices through the connector in response to the providing of the detection information. The connector provides the external host device with information of a communication type in which the controller communicates with the external host device, after the power is supplied. The communication type is one of a first communication type and a second communication type. The controller configures the connection terminals to correspond to a single or dual port based on a signal received from the external host device.
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公开(公告)号：US20180239696A1
公开(公告)日：2018-08-23
申请号：US15863218
申请日：2018-01-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Gwangman LIM , Eun-Jin YUN
CPC classification number: G06F12/0238 , G06F3/0625 , G06F3/0635 , G06F3/0679 , G06F12/0246 , G06F13/387 , G06F13/4081 , G06F13/4282 , G06F2212/202 , G06F2213/0026 , Y02D10/14 , Y02D10/151
Abstract: A storage device includes nonvolatile memory devices, a connector that includes connection terminals, and a controller that communicates with an external host device through the connector and to control the nonvolatile memory devices. The connector provides the external host device with detection information in response to the connector being connected with the external host device. Power is supplied from the external host device to the controller and the nonvolatile memory devices through the connector in response to the providing of the detection information. The connector provides the external host device with information of a communication type in which the controller communicates with the external host device, after the power is supplied. The communication type is one of a first communication type and a second communication type. The controller configures the connection terminals to correspond to a single or dual port based on a signal received from the external host device.
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Patent Agency Ranking
公开(公告)号：US20130265826A1
公开(公告)日：2013-10-10
申请号：US13738983
申请日：2013-01-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： ChulHo LEE , Eun-Jin YUN , BoGeun KIM
CPC classification number: G11C16/10 , G06F13/1694 , G11C11/1673 , G11C11/1675 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C16/26
Abstract: A memory system including a first memory of a first type; a second memory of a second type; and a controller configured to control the first memory and the second memory. The first type and second type are different, and the controller is configured to control the first memory and the second memory according to substantially the same command sequence.
Abstract translation: 一种存储器系统，包括第一类型的第一存储器; 第二种类型的第二存储器; 以及控制器，被配置为控制所述第一存储器和所述第二存储器。 第一类型和第二类型不同，并且控制器被配置为根据基本上相同的命令序列来控制第一存储器和第二存储器。
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公开(公告)号：US20200035278A1
公开(公告)日：2020-01-30
申请号：US16372223
申请日：2019-04-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung Joon KIM , Eun-Jin YUN , SANGHOAN CHANG
IPC: G11C8/10 , H03K19/173 , G11C7/22 , G11C16/08 , G11C16/26
Abstract: A nonvolatile memory device includes a control logic circuit that receives a read command from outside the nonvolatile memory device, a memory cell array which includes a plurality of memory cells connected to a plurality of word lines, an address generator that generates a plurality of addresses based on read information from the outside of the nonvolatile memory device, an address decoder sequentially selects a plurality of pages in at least one word line, which correspond to the plurality of addresses, a page buffer circuit that is connected to the memory cell array through a plurality of bit lines, and prepares a plurality of sequential data from memory cells connected to the selected pages by the address decoder, and an input/output circuit that continuously outputs the plurality of sequential data from the page buffer circuit to the outside of the nonvolatile memory device through data lines.
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公开(公告)号：US20180239684A1
公开(公告)日：2018-08-23
申请号：US15848793
申请日：2017-12-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Gwangman LIM , Eun-Jin YUN
CPC classification number: G06F11/328 , G06F11/3034 , G06F11/3044 , G06F11/325
Abstract: A storage device and a method for indicating a state of a storage device are provided. The storage device may include nonvolatile memory devices, a controller that controls the nonvolatile memory devices, a display device, and a display controller that controls the display device. The display controller may control the display device to display different colors respectively corresponding to states of the storage device. The states may include an access state in which the controller accesses the nonvolatile memory devices according to a request from an external host device, a standby state in which the controller is ready to perform the request from the external host device, a device fail state in which the controller and the nonvolatile memory devices cannot operate, and a replacement state in which the controller and the nonvolatile memory devices are selected for replacement.
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公开(公告)号：US20160110255A1
公开(公告)日：2016-04-21
申请号：US14800614
申请日：2015-07-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Eun-Jin YUN
CPC classification number: G11C29/52 , G06F11/1012 , G06F11/108 , G11C16/3418 , G11C2029/0411
Abstract: Provided are a data storage system, a data storage device and a RAID controller, which can control RAID operation and a RAID operating method of a memory device by transmitting a RAID configuration signal to the memory device. The data storage system includes a memory device that may include m nonvolatile memories, where m is a natural number, and a memory controller that may program data to at least the first to mth pages. The data storage system also includes a RAID controller that may generate a RAID configuration signal, including a RAID operation signal for determining whether to activate or deactivate a RAID operation of the memory device, and that may transmit the data and the RAID configuration signal to the memory controller. The memory controller may generate a RAID parity using first to (m−1)th data from the RAID controller and program the first to (m−1)th data to the first to (m−1)th pages and the RAID parity to the mth page when the RAID operation signal is activated, but program the first to mth data received from the RAID controller to the first to mth pages when the RAID operation signal is deactivated.
Abstract translation: 提供了一种数据存储系统，数据存储设备和RAID控制器，其可以通过向存储器件发送RAID配置信号来控制存储器件的RAID操作和RAID操作方法。 数据存储系统包括可以包括m个非自然数的m个非易失性存储器的存储器件，以及可以将数据编程到至少第一至第m页的存储器控制器。 数据存储系统还包括可以生成RAID配置信号的RAID控制器，包括用于确定是否激活或去激活存储器件的RAID操作的RAID操作信号，并且可以将数据和RAID配置信号发送到 内存控制器 存储器控制器可以使用来自RAID控制器的第一到第（m-1）个数据产生RAID奇偶校验，并且将第一到第（m-1）个数据编程到第一到第（m-1）页，并将RAID奇偶校验 当RAID操作信号被激活时的第m页，但是当RAID操作信号被去激活时，将从RAID控制器接收的第一到第m个数据编程到第一至第m页。
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公开(公告)号：US20230196753A1
公开(公告)日：2023-06-22
申请号：US18171579
申请日：2023-02-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Eun-Jin YUN , Sung-Joon Kim , Sang-Hoan Chang
IPC: G06V10/82 , G06V20/00 , G06F18/21 , G06F18/214 , G06V30/19 , G06V30/226
CPC classification number: G06V10/82 , G06V20/00 , G06F18/217 , G06F18/214 , G06V30/19173 , G06V30/2272
Abstract: An object recognition device including an artificial neural network (NN) engine configured to receive learning data and weights, make an object recognition model (ORM) learn by using the received information, and provide selected weight data including weights from the selected portion of the weights, and further configured to receive a feature vector, and apply the feature vector extracted from an object data that constructs the object and the selected weight data to the learned ORM to provide an object recognition result, a nonvolatile memory (NVM) configured to store the learned ORM, and an error correction code (ECC) engine configured to perform an ECC encoding on the selected weight data to generate parity data, provide the selected weight data and the parity data to the NVM, and provide the selected weight data to the NN engine by performing an ECC decoding on the selected weight data based on the parity data.
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