公开(公告)号：US20250133970A1

公开(公告)日：2025-04-24

申请号：US18444206

申请日：2024-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minwoo CHOI ,  Hajun SUNG ,  Bonwon KOO ,  Kiyeon YANG ,  Changseung LEE

IPC: H10N70/00 ,  G11C13/00 ,  H10B63/00

Abstract: Provided are a chalcogenide-based memory device capable of implementing multi-level memory and an electronic apparatus including the chalcogenide-based memory device. The memory device includes a first electrode and a second electrode arranged to be spaced apart from each other, and a memory layer provided between the first electrode and the second electrode and including a plurality of memory material layers having different threshold voltages from each other. Each of the plurality of memory material layers includes a chalcogenide-based material, has an ovonic threshold switching (OTS) characteristic, and is configured to have a threshold voltage varying depending on a polarity and intensity of an applied voltage.

公开(公告)号：US20250089270A1

公开(公告)日：2025-03-13

申请号：US18540222

申请日：2023-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiyeon YANG ,  Haeryong KIM ,  Hajun SUNG ,  Changseung LEE

IPC: H10B63/00 ,  H10B63/10

Abstract: Provided are a memory device, a manufacturing method thereof, and an electronic apparatus including the memory device. The memory device may include a plurality of first conductors arranged apart from each other and perpendicular to a substrate, a second conductor extending perpendicular to the substrate, a chalcogenide layer extending perpendicular to the substrate between the plurality of first conductors and the second conductor, and a plurality of first diffusion barrier layers selectively arranged only on the plurality of first conductors between the plurality of first conductors and the chalcogenide layer. The plurality of first diffusion barrier layers each may include a carbon-based material.

公开(公告)号：US20240324246A1

公开(公告)日：2024-09-26

申请号：US18594355

申请日：2024-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiyeon YANG ,  Donggeon GU ,  Bonwon KOO ,  Jeonghee PARK ,  Hajun SUNG ,  Dongho AHN ,  Zhe WU ,  Changseung LEE ,  Minwoo CHOI

IPC: H10B63/00 ,  H10N70/00

CPC classification number: H10B63/24 ,  H10B63/84 ,  H10N70/841 ,  H10N70/8825 ,  H10N70/8828

Abstract: Provided are a self-selecting memory device having polarity dependent threshold voltage shift characteristics and/or a memory apparatus including the self-selecting memory device. The memory device includes a first electrode, a second electrode apart from and facing the first electrode, and a memory layer between the first electrode and the second electrode. The memory layer has Ovonic threshold switching characteristics and is configured to have a threshold voltage of the memory layer be changed as a density of active traps in the memory layer is changed, the threshold voltage changing according to the polarity and the intensity of a bias voltage applied to the memory layer. Furthermore, an element composition distribution is configured to be maintained constant in the memory layer in response to the threshold voltage of the memory layer changing.

公开(公告)号：US20240032308A1

公开(公告)日：2024-01-25

申请号：US18478776

申请日：2023-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyoung YANG ,  Bonwon KOO ,  Chungman KIM ,  Kwangmin PARK ,  Hajun SUNG ,  Dongho AHN ,  Changseung LEE ,  Minwoo CHOI

IPC: H10B63/00 ,  G11C13/00 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/20 ,  H10N70/00

CPC classification number: H10B63/24 ,  G11C13/0004 ,  H10B61/10 ,  H10B63/84 ,  H10N50/01 ,  H10N50/80 ,  H10N70/24 ,  H10N70/25 ,  H10N70/063 ,  H10N70/231 ,  H10N70/8413 ,  H10N70/8825 ,  H10N70/8828 ,  H10N70/8833 ,  H10N70/8836

Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).

公开(公告)号：US20250098558A1

公开(公告)日：2025-03-20

申请号：US18828335

申请日：2024-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hajun SUNG ,  Minwoo CHOI ,  Youngjae KANG ,  Kiyeon YANG ,  Changseung LEE

IPC: H10N70/00 ,  G11C13/00 ,  H10B63/00

Abstract: A chalcogenide-based memory material may include a ternary semiconductor compound having a composition represented by XaY′bSec, wherein the chalcogenide-based memory material may have an ovonic threshold-switching (OTS) characteristic, and a threshold voltage of the chalcogenide-based memory material may change according to a polarity and an intensity of an applied voltage. In XaY′bSec, X≠Y, a+b+c=1, a>0.12, b>0.18, c≥0.4, and X and Y′ independently may be different ones of In, Sb, Ga, Sn, Al, Ge, Si, and P. A memory device may include the chalcogenide-based memory material. An electronic apparatus may include the memory device.

公开(公告)号：US20240147735A1

公开(公告)日：2024-05-02

申请号：US18187151

申请日：2023-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung HEO ,  Hajun SUNG ,  Seongyong PARK ,  Wooyoung YANG ,  Dongjin YUN

IPC: H10B63/00 ,  H10B61/00

CPC classification number: H10B63/24 ,  H10B61/10

Abstract: A switching device including a first electrode layer, a second electrode layer arranged to face the first electrode layer, and a selection layer arranged between the first electrode layer and the second electrode layer, wherein the first electrode layer is doped with at least one of manganese (Mn), iron (Fe), niobium (Nb), molybdenum (Mo), technetium (Tc), ruthenium (Ru), rhodium (Rh), hafnium (Hf), tantalum (Ta), tungsten (W), rhenium (Re), iridium (Ir), or platinum (Pt), may be provided.

公开(公告)号：US20230091136A1

公开(公告)日：2023-03-23

申请号：US17835508

申请日：2022-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiyeon YANG ,  Segab KWON ,  Hajun SUNG ,  Dongho AHN ,  Changseung LEE

IPC: H01L45/00 ,  H01L27/24

Abstract: Provided are a chalcogenide-based material, and a switching element and a memory device that include the same. The chalcogenide-based material includes: a chalcogenide material and a dopant. The chalcogenide material includes Ge, Sb, and Se. The dopant includes at least one metal or metalloid element selected from In, Al, Sr, and Si, an oxide of the metal or metalloid element, or a nitride of the metal or metalloid element.

公开(公告)号：US20250149084A1

公开(公告)日：2025-05-08

申请号：US18785752

申请日：2024-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseung LEE ,  Minwoo CHOI ,  Bonwon KOO ,  Hajun SUNG ,  Kiyeon YANG

IPC: G11C11/56 ,  H10B63/00 ,  H10B99/00

Abstract: Provided are a memory device for implementing a multi-level memory and a method of implementing a multi-level memory by using the memory device. The memory device includes first and second electrodes apart from each other, a self-selecting memory layer between the first and second electrodes having an ovonic threshold switching characteristic, including a chalcogenide-based material, and configured to have a threshold voltage varying depending on a polarity of and strength of a voltage applied thereto, and a resistive memory layer between the second electrode and the self-selecting memory layer and having a resistance characteristic varying depending on a voltage applied thereto. The memory device is configured to implement multi-level resistance states by changing at least one of a pulse polarity, a number of pulses, pulse height, and a pulse width of a voltage applied between the first and second electrodes.

公开(公告)号：US20240414926A1

公开(公告)日：2024-12-12

申请号：US18813539

申请日：2024-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyoung YANG ,  Bonwon KOO ,  Chungman KIM ,  Kwangmin PARK ,  Hajun SUNG ,  Dongho AHN ,  Changseung LEE ,  Minwoo CHOI

IPC: H10B63/00 ,  G11C13/00 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/00 ,  H10N70/20

Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).

公开(公告)号：US20230329007A1

公开(公告)日：2023-10-12

申请号：US18176750

申请日：2023-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hajun SUNG ,  Youngjae Kang ,  Bonwon Koo ,  Yongyoung Park ,  Dongho Ahn ,  Kiyeon Yang ,  Wooyoung Yang ,  Changseung Lee ,  Minwoo Choi

IPC: H10B63/00 ,  H10B61/00

CPC classification number: H10B63/24 ,  H10B61/10 ,  H10B63/80

Abstract: A chalcogenide material according to one embodiment includes germanium (Ge); arsenic (As); sulfur (S); selenium (Se), and at least one group III metal selected from indium (In), gallium (Ga), and aluminum (Al), wherein the content of the Ge may be greater than about 10 at % and less than or equal to about 30 at %, the content of the As may be greater than about 30 at % and less than or equal to about 50 at %, the content of Se is greater than about 20 at % and less than or equal to about 60 at %, the content of S is greater than about 0.5 at % and less than or equal to about 10 at %, and the content of the group III metal may be in the range of 0.5 at % to 10 at %.