公开(公告)号：US20150089327A1

公开(公告)日：2015-03-26

申请号：US14444856

申请日：2014-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Youn YOUN ,  Chul-Woo PARK ,  Hak-Soo YU

IPC: G06F11/16

CPC classification number: G11C29/886 ,  G06F11/1048 ,  G11C29/76

Abstract: The semiconductor memory device includes a memory cell array and an error correction code (ECC) circuit. The memory cell array is divided into a first memory region and a second memory region. Each of the first and second memory regions includes a plurality of pages each page including a plurality of memory cells connected to a word line. The ECC circuit corrects single-bit errors of the first memory region using parity bits. The first memory region provides a consecutive address space to an external device by correcting the single-bit errors using the ECC circuit and the second memory region is reserved for repairing at least one of a first failed page of the first memory region or a second failed page of the second memory region.

Abstract translation: 半导体存储器件包括存储单元阵列和纠错码（ECC）电路。 存储单元阵列被分成第一存储区和第二存储区。 第一和第二存储器区域中的每一个包括多个页面，每个页面包括连接到字线的多个存储器单元。 ECC电路使用奇偶校验位校正第一存储区域的单位错误。 第一存储器区域通过使用ECC电路校正单位错误来向外部设备提供连续的地址空间，并且第二存储器区域被保留用于修复第一存储器区域的第一故障页面或第二存储器区域中的至少一个 第二存储器区域的页面。

公开(公告)号：US20180081557A1

公开(公告)日：2018-03-22

申请号：US15685084

申请日：2017-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pavan Kumar KASIBHATLA ,  Hak-Soo YU ,  Seokin Hong

IPC: G06F3/06 ,  H04L12/28

CPC classification number: G06F3/0607 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0688 ,  H04L12/28 ,  H04L12/4625

Abstract: Disclosed is a computer system which includes a host and a memory module. The host transfers a plurality of cache lines to a memory module through a plurality of channels, the cache lines including a plurality of data elements and allocates cache lines with target data elements in the plurality of data elements to one channel of the plurality of channels. The target data elements are arranged within the ache lines according to a stride interval. The stride interval is a number of data elements between consecutive ones of the target data elements. The memory module includes gather-scatter engines that are respectively connected to the plurality of channels and scatter or gather the target data elements under control of the host.

公开(公告)号：US20140237177A1

公开(公告)日：2014-08-21

申请号：US14171343

申请日：2014-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hak-Soo YU ,  Chul-Woo PARK ,  Jung-Bae LEE

IPC: G11C11/406

CPC classification number: G11C11/40607 ,  G11C5/04 ,  G11C11/40611

Abstract: A memory module includes a master memory device and at least one slave memory device. The master memory device may generate a refresh clock signal, and perform a refresh operation in synchronization with the refresh clock signal. The slave memory device may be connected to receive the refresh clock signal, and perform a refresh operation in synchronization with the refresh clock signal.

Abstract translation: 存储器模块包括主存储器设备和至少一个从存储器设备。 主存储器件可以产生刷新时钟信号，并且与刷新时钟信号同步地执行刷新操作。 从存储器件可以被连接以接收刷新时钟信号，并且与刷新时钟信号同步地执行刷新操作。

公开(公告)号：US20150309743A1

公开(公告)日：2015-10-29

申请号：US14588496

申请日：2015-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Soo SOHN ,  Uk-Song KANG ,  KWANG-IL PARK ,  Chul-Woo PARK ,  Hak-Soo YU ,  Jae-Youn YOUN

IPC: G06F3/06

CPC classification number: G11C11/4087 ,  G11C5/025 ,  G11C7/02 ,  G11C11/4085

Abstract: A semiconductor memory device includes a control logic and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes a plurality of bank arrays, and each of the plurality of bank arrays includes a plurality of sub-arrays. The control logic controls an access to the memory cell array based on a command and an address signal. The control logic dynamically sets a keep-away zone that includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled. The first word-line is coupled to a first memory cell row of a first sub-array of the plurality of sub-arrays. Therefore, increased timing parameters may be compensated, and parallelism may be increased.

Abstract translation: 半导体存储器件包括控制逻辑和其中布置有多个存储器单元的存储单元阵列。 存储单元阵列包括多个存储体阵列，并且多个存储体阵列中的每一个包括多个子阵列。 控制逻辑基于命令和地址信号控制对存储器单元阵列的访问。 控制逻辑动态地设置包括在第一字线被启用时基于第一字线被去激活的多个存储器单元行的保留区。 第一字线耦合到多个子阵列中的第一子阵列的第一存储单元行。 因此，可以补偿增加的定时参数，并且可以增加并行性。

公开(公告)号：US20140268978A1

公开(公告)日：2014-09-18

申请号：US14144470

申请日：2013-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Jin CHOI ,  Su-A KIM ,  Young-Hoon SON ,  Jung-Ho AHN ,  Hak-Soo YU ,  Jae-Youn YOUN

IPC: G11C5/06

CPC classification number: G11C5/063 ,  G11C5/025 ,  G11C11/4093 ,  G11C11/4097 ,  G11C2207/105

Abstract: A semiconductor memory device may include a plurality of data input/output DQ pads and a plurality of first and second memory cell arrays. Each path of a first set of data paths from each of the plurality of first memory cell arrays to a corresponding DQ pad is physically shorter than each path of a second set of data paths from each of the plurality of second memory cell arrays to the corresponding DQ pad. Each of the plurality of first memory cell arrays is a designated first-speed access cell array and each of the plurality of second memory cell arrays is a designated second-speed access cell array, the second-speed being slower than the first-speed. A size of the each of the plurality of first memory cell arrays is smaller than a size of the each of the plurality of second memory cell arrays.

Abstract translation: 半导体存储器件可以包括多个数据输入/输出DQ焊盘和多个第一和第二存储单元阵列。 从多个第一存储器单元阵列中的每一个到相应的DQ焊盘的第一组数据路径的每个路径物理上比从多个第二存储单元阵列中的每一个到相应的第二组数据路径的第二组数据路径的每个路径短 DQ垫。 多个第一存储单元阵列中的每一个是指定的第一速度存取单元阵列，并且多个第二存储单元阵列中的每一个是指定的第二速度存取单元阵列，第二速度比第一速度慢。 多个第一存储单元阵列中的每一个的大小小于多个第二存储单元阵列中的每一个的大小。

公开(公告)号：US20140219042A1

公开(公告)日：2014-08-07

申请号：US14168793

申请日：2014-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hak-Soo YU ,  Jung-Bae LEE

IPC: G11C11/406

CPC classification number: G11C11/406 ,  G11C11/40603

Abstract: In a method of refreshing in a memory device having a plurality of pages, a candidate refresh address corresponding to a page scheduled to be refreshed after a monitoring period is generated. Whether an active command is processed for the candidate refresh address is monitored during the monitoring period. If an active command is processed for the candidate refresh address during the monitoring period, the scheduled refresh for that page is skipped. If no active command is processed for the candidate refresh address during the monitoring period, the scheduled refresh operation is performed.

Abstract translation: 在具有多个页面的存储装置中进行刷新的方法中，生成与在监视期间之后被更新的页面对应的候补刷新地址。 在监视期间监视是否处理候选刷新地址的活动命令。 如果在监视期间处理候选刷新地址的活动命令，则跳过该页面的计划刷新。 如果在监视期间没有处理候选刷新地址的活动命令，则执行预定的刷新操作。

公开(公告)号：US20210150319A1

公开(公告)日：2021-05-20

申请号：US16892637

申请日：2020-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hak-Soo YU ,  Nam Sung KIM ,  Kyomin SOHN ,  Jaeyoun YOUN

IPC: G06N3/063 ,  G11C11/54 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/56 ,  G11C11/4091 ,  G06N3/08

Abstract: A neuromorphic device includes a memory cell array that includes first memory cells corresponding to a first address and storing first weights and second memory cells corresponding to a second address and storing second weights, and a neuron circuit that includes an integrator summing first read signals from the first memory cells and an activation circuit outputting a first activation signal based on a first sum signal of the first read signals output from the integrator.

公开(公告)号：US20150155055A1

公开(公告)日：2015-06-04

申请号：US14462843

申请日：2014-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sua KIM ,  Dongsoo KANG ,  Chulwoo PARK ,  Jun Hee YOO ,  Hak-Soo YU ,  Jaeyoun YOUN ,  Sung Hyun LEE ,  Jinsu JUNG ,  Hyojin CHOI

IPC: G11C29/04 ,  G11C17/16

CPC classification number: G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C2029/4402

Abstract: A test method of the semiconductor memory device including a memory cell array and an anti-fuse array includes detecting failed cells included in the memory cell array; determining a fail address corresponding to the detected failed cells; storing the determined fail address in a first region of the memory cell array; and reading the fail address stored in the first region to program the read fail address in the anti-fuse array. According to the test method of a semiconductor memory device and the semiconductor memory system, since the test operation can be performed without an additional memory for storing an address, the semiconductor memory device and the test circuit can be embodied by a small area.

Abstract translation: 包括存储单元阵列和反熔丝阵列的半导体存储器件的测试方法包括检测包括在存储单元阵列中的故障单元; 确定与检测到的故障小区相对应的故障地址; 将所确定的故障地址存储在所述存储单元阵列的第一区域中; 并读取存储在第一区域中的故障地址，以对反熔丝阵列中的读故障地址进行编程。 根据半导体存储器件和半导体存储器系统的测试方法，由于可以在没有用于存储地址的附加存储器的情况下执行测试操作，所以半导体存储器件和测试电路可以被小面积体现。

公开(公告)号：US20150134895A1

公开(公告)日：2015-05-14

申请号：US14465995

申请日：2014-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Soo SOHN ,  Chul-Woo PARK ,  Kwang-Il PARK ,  Hak-Soo YU

IPC: G11C14/00 ,  G11C11/00

CPC classification number: G11C14/0018 ,  G11C11/40 ,  G11C29/702 ,  G11C29/785 ,  G11C2029/4402

Abstract: A semiconductor memory device may include a cell array comprising a plurality of memory cells, each memory cell connected to a word line and a bit line, the cell array divided into a plurality of blocks, each block including a plurality of word lines, the plurality of blocks including at least a first defective block; a nonvolatile storage circuit configured to store address information of the first defective block, and to output the address information to an external device; and a fuse circuit configured to cut off an activation of word lines of the first defective block.

Abstract translation: 半导体存储器件可以包括包括多个存储器单元的单元阵列，每个存储器单元连接到字线和位线，单元阵列被划分成多个块，每个块包括多个字线，多个字线 的至少包括第一缺陷块的块; 非易失性存储电路，被配置为存储所述第一缺陷块的地址信息，并将所述地址信息输出到外部设备; 以及熔丝电路，被配置为切断第一有缺陷块的字线的激活。

公开(公告)号：US20140149652A1

公开(公告)日：2014-05-29

申请号：US14090510

申请日：2013-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Woo PARK ,  Dong-Soo KANG ,  Su-A KIM ,  Jun-hee YOO ,  Hak-Soo YU ,  Jae-Youn YOUN ,  Sung-hyun LEE ,  Kyoung-Heon JEONG ,  Hyo-Jin CHOI ,  Young-Soo SOHN

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G06F12/0223 ,  G06F12/0292 ,  G11C29/76 ,  G11C29/84

Abstract: In one example embodiment, a memory system includes a memory module and a memory controller. The memory module is configured generate density information of the memory module based on a number of the bad pages of the memory module, the bad pages being pages that have a fault. The memory controller is configured to map a continuous physical address to a dynamic random access memory (dram) address of the memory module based on the density information received from the memory module.

Abstract translation: 在一个示例性实施例中，存储器系统包括存储器模块和存储器控制器。 配置存储器模块基于存储器模块的不良页面的数量生成存储器模块的密度信息，坏页面是具有故障的页面。 存储器控制器被配置为基于从存储器模块接收的密度信息将连续的物理地址映射到存储器模块的动态随机存取存储器（显存）地址。