公开(公告)号：US20240404570A1

公开(公告)日：2024-12-05

申请号：US18581187

申请日：2024-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Seok PARK ,  Do-Han KIM ,  Minsu BAE ,  Chang-Hyun BAE ,  Young-Hoon SON ,  Hye-Seung YU ,  Yoenhwa LEE ,  Daihyun LIM ,  Insu CHOI ,  Kideok HAN

IPC: G11C7/22 ,  G11C7/10

Abstract: A method of training a memory device is provided. In first to third DCA training steps, a score for each of first to third DCA code combinations is calculated based on an eye window size of a data signal, and in response to a tie occurring among scores, a DCA code combination is selected based on the sum of an even-eye window minimum value and an odd-eye window minimum value of the data signal.

公开(公告)号：US20170219647A1

公开(公告)日：2017-08-03

申请号：US15295244

申请日：2016-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Joo YUN ,  Sukyong KANG ,  Hye-Seung YU ,  Hyunui LEE

IPC: G01R31/28 ,  G01R31/02 ,  H01L25/065 ,  G01R31/26 ,  H03K17/687 ,  H01L21/66

CPC classification number: G01R31/2853 ,  G01R31/025 ,  G01R31/26 ,  G01R31/2884 ,  G11C5/025 ,  G11C29/006 ,  G11C29/025 ,  G11C29/50008 ,  H01L22/14 ,  H01L22/34 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06596 ,  H01L2924/15311 ,  H03K17/6872

Abstract: Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.

公开(公告)号：US20170345754A1

公开(公告)日：2017-11-30

申请号：US15396633

申请日：2016-12-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Joo YUN ,  Suk-Yong KANG ,  Sang-Hoon SHIN ,  Hye-Seung YU ,  Hyun-Ui LEE ,  Jae-Hun JUNG

IPC: H01L23/522 ,  H01L23/525 ,  H01L25/065 ,  H02J50/12 ,  H01L23/528 ,  H01L23/48

CPC classification number: H01L23/5227 ,  H01F27/2804 ,  H01F38/14 ,  H01F2027/2809 ,  H01F2038/143 ,  H01L23/481 ,  H01L23/5256 ,  H01L23/528 ,  H01L25/0657 ,  H01L2225/06524 ,  H01L2225/06541 ,  H02J50/12 ,  H04B5/0037 ,  H04B5/0075 ,  H05K1/0306 ,  H05K1/165 ,  H05K3/4629 ,  H05K2201/09709 ,  H05K2201/09845 ,  H05K2201/10098 ,  H05K2201/10159 ,  H05K2201/10181

Abstract: A three-dimensional (3D) inductor structure comprising: a first semiconductor die including: a first conductive pattern; and a second conductive pattern spaced apart from the first conductive pattern; a second semiconductor die stacked on the first semiconductor die, the second semiconductor die including: a third conductive pattern; a fourth conductive pattern spaced apart from the third conductive pattern; a first through-substrate via (TSV) penetrating the second semiconductor die and electrically connecting the first conductive pattern with the third conductive pattern; and a second TSV penetrating the second semiconductor die and electrically connecting the second conductive pattern with the fourth conductive pattern, and a first conductive connection pattern included in the first semiconductor die and electrically connecting a first end of the first conductive pattern with a first end of the second conductive pattern, or included in the second semiconductor die and electrically connecting a first end of the third conductive pattern with a first end of the fourth conductive pattern.

公开(公告)号：US20190165808A1

公开(公告)日：2019-05-30

申请号：US16262127

申请日：2019-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Seung YU ,  Sukyong KANG ,  Wonjoo YUN ,  Hyunui LEE ,  Jae-Hun JUNG

IPC: H03M13/09 ,  H03M13/00 ,  G11C29/52 ,  G06F11/10

Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.

公开(公告)号：US20170331493A1

公开(公告)日：2017-11-16

申请号：US15488789

申请日：2017-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Seung YU ,  Sukyong KANG ,  Wonjoo YUN ,  Hyunui LEE ,  Jae-Hun JUNG

IPC: H03M13/09 ,  G06F11/10 ,  G11C29/52 ,  H03M13/00

CPC classification number: H03M13/098 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/52 ,  H03M13/611

Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.

公开(公告)号：US20150194195A1

公开(公告)日：2015-07-09

申请号：US14505614

申请日：2014-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-Seung YU ,  Jun-Bae KIM

IPC: G11C7/10 ,  G11C7/22 ,  H03K17/041

CPC classification number: H03K17/04106 ,  G11C5/147 ,  G11C7/1084

Abstract: A self bias buffer circuit includes a buffer and bias controller. The buffer provides a self bias voltage based on a reference voltage and to be driven based on the self bias voltage. The buffer also generates an output signal based on a comparison of an input signal and the reference voltage. The bias controller adjusts the self bias voltage based on the reference voltage.

Abstract translation: 自偏置缓冲电路包括缓冲器和偏置控制器。 缓冲器基于参考电压提供自偏压，并且基于自偏压驱动。 缓冲器还基于输入信号和参考电压的比较产生输出信号。 偏置控制器根据参考电压调节自偏置电压。