公开(公告)号：US20170012025A1

公开(公告)日：2017-01-12

申请号：US15274453

申请日：2016-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heung-Kyu KWON ,  Jong-Kook KIM ,  Ji-Chul KIM ,  Byeong-Yeon CHO

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H01L21/66 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L22/10 ,  H01L22/14 ,  H01L23/3128 ,  H01L23/488 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L24/45 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85005 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor package including a mounting substrate, a first semiconductor chip mounted on an upper surface of the mounting substrate, a unit package stacked on the first semiconductor chip may be provided. The unit package includes a package substrate and a second semiconductor chip mounted on the package substrate. A plurality of bonding wires connects bonding pads of the mounting substrate and connection pads of the unit package, thereby electrically connecting the first and second semiconductor chips to each other. A molding member is provided on the mounting substrate to cover the first semiconductor chip and the unit package.

Abstract translation: 可以提供包括安装基板，安装在安装基板的上表面上的第一半导体芯片，堆叠在第一半导体芯片上的单元封装的半导体封装。 单元封装包括封装衬底和安装在封装衬底上的第二半导体芯片。 多个接合线连接安装基板的接合焊盘和单元封装的连接焊盘，从而将第一和第二半导体芯片彼此电连接。 在安装基板上设置成型部件，以覆盖第一半导体芯片和单元封装。

公开(公告)号：US20130256916A1

公开(公告)日：2013-10-03

申请号：US13756724

申请日：2013-02-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heung-Kyu KWON ,  Jong-Kook KIM ,  Ji-Chul KIM ,  Byeong-Yeon CHO

IPC: H01L23/488

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L22/10 ,  H01L22/14 ,  H01L23/3128 ,  H01L23/488 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L24/45 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85005 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor package including a mounting substrate, a first semiconductor chip mounted on an upper surface of the mounting substrate, a unit package stacked on the first semiconductor chip may be provided. The unit package includes a package substrate and a second semiconductor chip mounted on the package substrate. A plurality of bonding wires connects bonding pads of the mounting substrate and connection pads of the unit package, thereby electrically connecting the first and second semiconductor chips to each other. A molding member is provided on the mounting substrate to cover the first semiconductor chip and the unit package.

Abstract translation: 可以提供包括安装基板，安装在安装基板的上表面上的第一半导体芯片，堆叠在第一半导体芯片上的单元封装的半导体封装。 单元封装包括封装衬底和安装在封装衬底上的第二半导体芯片。 多个接合线连接安装基板的接合焊盘和单元封装的连接焊盘，从而将第一和第二半导体芯片彼此电连接。 在安装基板上设置模制构件以覆盖第一半导体芯片和单元封装。

公开(公告)号：US20140239300A1

公开(公告)日：2014-08-28

申请号：US14068091

申请日：2013-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mi-Na CHOI ,  Ji-Chul KIM ,  Se-Ran BAE ,  Eun-Seok CHO ,  Hee-Jung HWANG

IPC: H01L21/66

CPC classification number: H01L23/345 ,  G01R31/2875 ,  H01L22/34 ,  H01L23/34 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Semiconductor test devices and methods for fabricating the same may be provided. The semiconductor test device may include a first thermal test flip chip cell including a first heater and a first sensor, and a test substrate formed under the first thermal test flip chip cell. The first thermal test flip chip cell may include a plurality of first bumps arranged on a bottom surface of the first thermal test flip chip cell and be configured to be electrically connected to the first heater and the first sensor. The test substrate may include a first ball array arranged on a bottom surface of the test substrate in a first direction and be configured to be electrically connected to the plurality of first bumps, which are electrically connected to the first heater and the first sensor.

Abstract translation: 可以提供半导体测试装置及其制造方法。 半导体测试装置可以包括第一热测试倒装芯片单元，其包括第一加热器和第一传感器，以及形成在第一热测试倒装芯片单元下的测试基板。 第一热测试倒装芯片单元可以包括布置在第一热测试倒装芯片单元的底表面上的多个第一凸块，并且被配置为电连接到第一加热器和第一传感器。 测试基板可以包括在第一方向上布置在测试基板的底表面上的第一球阵列，并且被配置为电连接到电连接到第一加热器和第一传感器的多个第一凸块。

公开(公告)号：US20140167245A1

公开(公告)日：2014-06-19

申请号：US14106912

申请日：2013-12-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Deuk KIM ,  Ji-Chul KIM

IPC: H01L23/36

CPC classification number: H01L23/36 ,  H01L21/563 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/49894 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A semiconductor package includes a flexible base film having a first surface opposing a second surface, a semiconductor chip mounted on the first surface of the base film, and a touch sensing structure including at least one conductive pattern adjacent to the semiconductor chip. The at least one conductive pattern is disposed through the base film and has a surface exposed at the second surface of the base film. A contact condition of the semiconductor package is determined based on detection of a conductive path between the at least one conductive pattern and a conductive frame or support surface of the semiconductor package. The contact condition provides an indication of heat dissipation that may be expected to occur for the chip during operation.

Abstract translation: 半导体封装包括具有与第二表面相对的第一表面的柔性基膜，安装在基膜的第一表面上的半导体芯片，以及包括与半导体芯片相邻的至少一个导电图案的触摸感测结构。 所述至少一个导电图案设置穿过所述基底膜并具有在所述基底膜的第二表面处露出的表面。 基于对至少一个导电图案和半导体封装的导电框架或支撑表面之间的导电路径的检测来确定半导体封装的接触状态。 接触条件提供可能预期在操作期间芯片发生的散热的指示。